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Commit 9a85dad1 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Rename CTI nodes to lower case on sdm845 and sdm670"

parents 015e9c97 38186367

arch/arm64/boot/dts/qcom/sdm670-coresight.dtsi

+22 −22
Original line number Diff line number Diff line
@@ -1336,7 +1336,7 @@ 
		reg = <0x69e1000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-ddr0";

		coresight-name = "coresight-cti-ddr_dl_0_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1348,7 +1348,7 @@ 
		reg = <0x69e4000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-ddr1";

		coresight-name = "coresight-cti-ddr_dl_1_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1360,7 +1360,7 @@ 
		reg = <0x69e5000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1-ddr1";

		coresight-name = "coresight-cti-ddr_dl_1_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1372,7 +1372,7 @@ 
		reg = <0x6c09000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-dlmm";

		coresight-name = "coresight-cti-dlmm_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1384,7 +1384,7 @@ 
		reg = <0x6c0a000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1-dlmm";

		coresight-name = "coresight-cti-dlmm_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1396,7 +1396,7 @@ 
		reg = <0x6c29000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-dlct";

		coresight-name = "coresight-cti-dlct_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1408,7 +1408,7 @@ 
		reg = <0x6c2a000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1-dlct";

		coresight-name = "coresight-cti-dlct_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1420,7 +1420,7 @@ 
		reg = <0x69a4000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-wcss";

		coresight-name = "coresight-cti-wcss_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1432,7 +1432,7 @@ 
		reg = <0x69a5000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1-wcss";

		coresight-name = "coresight-cti-wcss_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1444,7 +1444,7 @@ 
		reg = <0x69a6000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti2-wcss";

		coresight-name = "coresight-cti-wcss_cti2";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1480,7 +1480,7 @@ 
		reg = <0x6b10000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti2-ssc_sdc";

		coresight-name = "coresight-cti-ssc_sdc_cti2";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1492,7 +1492,7 @@ 
		reg = <0x6b11000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1-ssc";

		coresight-name = "coresight-cti-ssc_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1504,7 +1504,7 @@ 
		reg = <0x6b1b000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-ssc-q6";

		coresight-name = "coresight-cti-ssc_q6_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1516,7 +1516,7 @@ 
		reg = <0x6b1e000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-ssc-noc";

		coresight-name = "coresight-cti-ssc_noc";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1528,7 +1528,7 @@ 
		reg = <0x6b1f000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti6-ssc-noc";

		coresight-name = "coresight-cti-ssc_noc_cti6";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1540,7 +1540,7 @@ 
		reg = <0x6b04000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-swao";

		coresight-name = "coresight-cti-swao_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1552,7 +1552,7 @@ 
		reg = <0x6b05000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1-swao";

		coresight-name = "coresight-cti-swao_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1564,7 +1564,7 @@ 
		reg = <0x6b06000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti2-swao";

		coresight-name = "coresight-cti-swao_cti2";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1576,7 +1576,7 @@ 
		reg = <0x6b07000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti3-swao";

		coresight-name = "coresight-cti-swao_cti3";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1624,7 +1624,7 @@ 
		reg = <0x78e0000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-apss";

		coresight-name = "coresight-cti-apss_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1636,7 +1636,7 @@ 
		reg = <0x78f0000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1-apss";

		coresight-name = "coresight-cti-apss_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1648,7 +1648,7 @@ 
		reg = <0x7900000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti2-apss";

		coresight-name = "coresight-cti-apss_cti2";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi

+9 −9
Original line number Diff line number Diff line
@@ -1584,7 +1584,7 @@ 
		reg = <0x69e1000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-DDR_DL_0_CTI";

		coresight-name = "coresight-cti-ddr_dl_0_cti";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1596,7 +1596,7 @@ 
		reg = <0x69e4000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-DDR_DL_1_CTI0";

		coresight-name = "coresight-cti-ddr_dl_1_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1608,7 +1608,7 @@ 
		reg = <0x69e5000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-DDR_DL_1_CTI1";

		coresight-name = "coresight-cti-ddr_dl_1_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1620,7 +1620,7 @@ 
		reg = <0x6c09000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-DLMM_CTI0";

		coresight-name = "coresight-cti-dlmm_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1632,7 +1632,7 @@ 
		reg = <0x6c0a000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-DLMM_CTI1";

		coresight-name = "coresight-cti-dlmm_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1644,7 +1644,7 @@ 
		reg = <0x78e0000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-APSS_CTI0";

		coresight-name = "coresight-cti-apss_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1656,7 +1656,7 @@ 
		reg = <0x78f0000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-APSS_CTI1";

		coresight-name = "coresight-cti-apss_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1668,7 +1668,7 @@ 
		reg = <0x7900000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-APSS_CTI2";

		coresight-name = "coresight-cti-apss_cti2";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1996,7 +1996,7 @@ 
		reg = <0x6b04000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-SWAO_CTI0";

		coresight-name = "coresight-cti-swao_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";