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Commit 38186367 authored by Pratik Patel's avatar Pratik Patel Committed by Saranya Chidura
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ARM: dts: msm: Rename CTI nodes to lower case on sdm845 and sdm670 



Rename CTI nodes in device tree of SDM845 and SDM670 to lower case
to help with consistent tool usage.

Change-Id: I73c8e23370b4e123b4cb1ec62b7045c00fa00ed1
Signed-off-by: default avatarPratik Patel <pratikp@codeaurora.org>
Signed-off-by: default avatarSaranya Chidura <schidura@codeaurora.org>
parent 902b1499

arch/arm64/boot/dts/qcom/sdm670-coresight.dtsi

+22 −22
Original line number Diff line number Diff line
@@ -1308,7 +1308,7 @@ 
		reg = <0x69e1000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-ddr0";

		coresight-name = "coresight-cti-ddr_dl_0_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1320,7 +1320,7 @@ 
		reg = <0x69e4000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-ddr1";

		coresight-name = "coresight-cti-ddr_dl_1_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1332,7 +1332,7 @@ 
		reg = <0x69e5000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1-ddr1";

		coresight-name = "coresight-cti-ddr_dl_1_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1344,7 +1344,7 @@ 
		reg = <0x6c09000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-dlmm";

		coresight-name = "coresight-cti-dlmm_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1356,7 +1356,7 @@ 
		reg = <0x6c0a000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1-dlmm";

		coresight-name = "coresight-cti-dlmm_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1368,7 +1368,7 @@ 
		reg = <0x6c29000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-dlct";

		coresight-name = "coresight-cti-dlct_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1380,7 +1380,7 @@ 
		reg = <0x6c2a000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1-dlct";

		coresight-name = "coresight-cti-dlct_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1391,7 +1391,7 @@ 
		reg = <0x69a4000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-wcss";

		coresight-name = "coresight-cti-wcss_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1402,7 +1402,7 @@ 
		reg = <0x69a5000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1-wcss";

		coresight-name = "coresight-cti-wcss_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1413,7 +1413,7 @@ 
		reg = <0x69a6000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti2-wcss";

		coresight-name = "coresight-cti-wcss_cti2";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1446,7 +1446,7 @@ 
		reg = <0x6b10000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti2-ssc_sdc";

		coresight-name = "coresight-cti-ssc_sdc_cti2";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1457,7 +1457,7 @@ 
		reg = <0x6b11000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1-ssc";

		coresight-name = "coresight-cti-ssc_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1468,7 +1468,7 @@ 
		reg = <0x6b1b000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-ssc-q6";

		coresight-name = "coresight-cti-ssc_q6_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1479,7 +1479,7 @@ 
		reg = <0x6b1e000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-ssc-noc";

		coresight-name = "coresight-cti-ssc_noc";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1490,7 +1490,7 @@ 
		reg = <0x6b1f000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti6-ssc-noc";

		coresight-name = "coresight-cti-ssc_noc_cti6";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1501,7 +1501,7 @@ 
		reg = <0x6b04000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-swao";

		coresight-name = "coresight-cti-swao_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1512,7 +1512,7 @@ 
		reg = <0x6b05000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1-swao";

		coresight-name = "coresight-cti-swao_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1523,7 +1523,7 @@ 
		reg = <0x6b06000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti2-swao";

		coresight-name = "coresight-cti-swao_cti2";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1534,7 +1534,7 @@ 
		reg = <0x6b07000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti3-swao";

		coresight-name = "coresight-cti-swao_cti3";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1578,7 +1578,7 @@ 
		reg = <0x78e0000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-apss";

		coresight-name = "coresight-cti-apss_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1589,7 +1589,7 @@ 
		reg = <0x78f0000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1-apss";

		coresight-name = "coresight-cti-apss_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1600,7 +1600,7 @@ 
		reg = <0x7900000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti2-apss";

		coresight-name = "coresight-cti-apss_cti2";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi

+9 −9
Original line number Diff line number Diff line
@@ -1556,7 +1556,7 @@ 
		reg = <0x69e1000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-DDR_DL_0_CTI";

		coresight-name = "coresight-cti-ddr_dl_0_cti";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1568,7 +1568,7 @@ 
		reg = <0x69e4000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-DDR_DL_1_CTI0";

		coresight-name = "coresight-cti-ddr_dl_1_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1580,7 +1580,7 @@ 
		reg = <0x69e5000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-DDR_DL_1_CTI1";

		coresight-name = "coresight-cti-ddr_dl_1_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1592,7 +1592,7 @@ 
		reg = <0x6c09000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-DLMM_CTI0";

		coresight-name = "coresight-cti-dlmm_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1604,7 +1604,7 @@ 
		reg = <0x6c0a000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-DLMM_CTI1";

		coresight-name = "coresight-cti-dlmm_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1616,7 +1616,7 @@ 
		reg = <0x78e0000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-APSS_CTI0";

		coresight-name = "coresight-cti-apss_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1628,7 +1628,7 @@ 
		reg = <0x78f0000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-APSS_CTI1";

		coresight-name = "coresight-cti-apss_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1640,7 +1640,7 @@ 
		reg = <0x7900000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-APSS_CTI2";

		coresight-name = "coresight-cti-apss_cti2";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1968,7 +1968,7 @@ 
		reg = <0x6b04000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-SWAO_CTI0";

		coresight-name = "coresight-cti-swao_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";