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Commit 9981b037 authored by Subhash Jadavani's avatar Subhash Jadavani Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: add UFS ref_clk support on SDM845 



This change adds the UFS ref_clk for both the UFS host controllers
instances on SDM845.

Change-Id: I208716c694aaa2038a79820f29c63cfd48604539
Signed-off-by: default avatarSubhash Jadavani <subhashj@codeaurora.org>
parent 1cc8f320

arch/arm64/boot/dts/qcom/sdm845.dtsi

+14 −8
Original line number Diff line number Diff line
@@ -892,10 +892,11 @@ 
		reg-names = "phy_mem";

		#phy-cells = <0>;



		/* TODO: add "ref_clk_src" */

		clock-names = "ref_clk",

		clock-names = "ref_clk_src",

			"ref_clk",

			"ref_aux_clk";

		clocks = <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,

		clocks = <&clock_rpmh RPMH_LN_BB_CLK1>,

			<&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,

			<&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;



		status = "disabled";
@@ -911,13 +912,13 @@ 
		lanes-per-direction = <2>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */



		/* TODO: add "ref_clk" */

		clock-names =

			"core_clk",

			"bus_aggr_clk",

			"iface_clk",

			"core_clk_unipro",

			"core_clk_ice",

			"ref_clk",

			"tx_lane0_sync_clk",

			"rx_lane0_sync_clk",

			"rx_lane1_sync_clk";
@@ -928,6 +929,7 @@ 
			<&clock_gcc GCC_UFS_PHY_AHB_CLK>,

			<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

			<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,

			<&clock_rpmh RPMH_LN_BB_CLK1>,

			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
@@ -939,6 +941,7 @@ 
			<75000000 300000000>,

			<0 0>,

			<0 0>,

			<0 0>,

			<0 0>;



		qcom,msm-bus,name = "ufshc_mem";
@@ -984,10 +987,11 @@ 
		reg-names = "phy_mem";

		#phy-cells = <0>;



		/* TODO: add "ref_clk_src" */

		clock-names = "ref_clk",

		clock-names = "ref_clk_src",

			"ref_clk",

			"ref_aux_clk";

		clocks = <&clock_gcc GCC_UFS_CARD_CLKREF_CLK>,

		clocks = <&clock_rpmh RPMH_LN_BB_CLK1>,

			<&clock_gcc GCC_UFS_CARD_CLKREF_CLK>,

			<&clock_gcc GCC_UFS_CARD_PHY_AUX_CLK>;



		status = "disabled";
@@ -1003,13 +1007,13 @@ 
		lanes-per-direction = <1>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */



		/* TODO: add "ref_clk" */

		clock-names =

			"core_clk",

			"bus_aggr_clk",

			"iface_clk",

			"core_clk_unipro",

			"core_clk_ice",

			"ref_clk",

			"tx_lane0_sync_clk",

			"rx_lane0_sync_clk";

		/* TODO: add HW CTL clocks when available */
@@ -1019,6 +1023,7 @@ 
			<&clock_gcc GCC_UFS_CARD_AHB_CLK>,

			<&clock_gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,

			<&clock_gcc GCC_UFS_CARD_ICE_CORE_CLK>,

			<&clock_rpmh RPMH_LN_BB_CLK1>,

			<&clock_gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>;

		freq-table-hz =
@@ -1028,6 +1033,7 @@ 
			<37500000 150000000>,

			<75000000 300000000>,

			<0 0>,

			<0 0>,

			<0 0>;



		qcom,msm-bus,name = "ufshc_card";