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Commit 1cc8f320 authored by Subhash Jadavani's avatar Subhash Jadavani Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: fix the UFS master/slave ids for bus voting on SDM845 



Now that we have 2 different instances of UFS controllers on SDM845, we
are having different master/slave ids for both these instances. This
change adds the appropriate master/slave ids for them.

Change-Id: I907f33f677edb37c530843f79e7ea130d61052a1
Signed-off-by: default avatarSubhash Jadavani <subhashj@codeaurora.org>
parent 42f79ace

arch/arm64/boot/dts/qcom/sdm845.dtsi

+31 −31
Original line number Diff line number Diff line
@@ -945,28 +945,28 @@ 
		qcom,msm-bus,num-cases = <22>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-KBps =

		<95 512 0 0>, <1 650 0 0>,          /* No vote */

		<95 512 922 0>, <1 650 1000 0>,     /* PWM G1 */

		<95 512 1844 0>, <1 650 1000 0>,    /* PWM G2 */

		<95 512 3688 0>, <1 650 1000 0>,    /* PWM G3 */

		<95 512 7376 0>, <1 650 1000 0>,    /* PWM G4 */

		<95 512 1844 0>, <1 650 1000 0>,    /* PWM G1 L2 */

		<95 512 3688 0>, <1 650 1000 0>,    /* PWM G2 L2 */

		<95 512 7376 0>, <1 650 1000 0>,    /* PWM G3 L2 */

		<95 512 14752 0>, <1 650 1000 0>,   /* PWM G4 L2 */

		<95 512 127796 0>, <1 650 1000 0>,  /* HS G1 RA */

		<95 512 255591 0>, <1 650 1000 0>,  /* HS G2 RA */

		<95 512 511181 0>, <1 650 1000 0>,  /* HS G3 RA */

		<95 512 255591 0>, <1 650 1000 0>,  /* HS G1 RA L2 */

		<95 512 511181 0>, <1 650 1000 0>,  /* HS G2 RA L2 */

		<95 512 1022362 0>, <1 650 1000 0>, /* HS G3 RA L2 */

		<95 512 149422 0>, <1 650 1000 0>,  /* HS G1 RB */

		<95 512 298189 0>, <1 650 1000 0>,  /* HS G2 RB */

		<95 512 596378 0>, <1 650 1000 0>,  /* HS G3 RB */

		<95 512 298189 0>, <1 650 1000 0>,  /* HS G1 RB L2 */

		<95 512 596378 0>, <1 650 1000 0>,  /* HS G2 RB L2 */

		<95 512 1192756 0>, <1 650 1000 0>, /* HS G3 RB L2 */

		<95 512 4096000 0>, <1 650 1000 0>; /* Max. bandwidth */

		<123 512 0 0>, <1 757 0 0>,          /* No vote */

		<123 512 922 0>, <1 757 1000 0>,     /* PWM G1 */

		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G2 */

		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G3 */

		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G4 */

		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G1 L2 */

		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G2 L2 */

		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G3 L2 */

		<123 512 14752 0>, <1 757 1000 0>,   /* PWM G4 L2 */

		<123 512 127796 0>, <1 757 1000 0>,  /* HS G1 RA */

		<123 512 255591 0>, <1 757 1000 0>,  /* HS G2 RA */

		<123 512 511181 0>, <1 757 1000 0>,  /* HS G3 RA */

		<123 512 255591 0>, <1 757 1000 0>,  /* HS G1 RA L2 */

		<123 512 511181 0>, <1 757 1000 0>,  /* HS G2 RA L2 */

		<123 512 1022362 0>, <1 757 1000 0>, /* HS G3 RA L2 */

		<123 512 149422 0>, <1 757 1000 0>,  /* HS G1 RB */

		<123 512 298189 0>, <1 757 1000 0>,  /* HS G2 RB */

		<123 512 596378 0>, <1 757 1000 0>,  /* HS G3 RB */

		<123 512 298189 0>, <1 757 1000 0>,  /* HS G1 RB L2 */

		<123 512 596378 0>, <1 757 1000 0>,  /* HS G2 RB L2 */

		<123 512 1192756 0>, <1 757 1000 0>, /* HS G3 RB L2 */

		<123 512 4096000 0>, <1 757 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",

		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
@@ -1034,15 +1034,15 @@ 
		qcom,msm-bus,num-cases = <9>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-KBps =

		<95 512 0 0>, <1 650 0 0>,          /* No vote */

		<95 512 922 0>, <1 650 1000 0>,     /* PWM G1 */

		<95 512 127796 0>, <1 650 1000 0>,  /* HS G1 RA */

		<95 512 255591 0>, <1 650 1000 0>,  /* HS G2 RA */

		<95 512 511181 0>, <1 650 1000 0>,  /* HS G3 RA */

		<95 512 149422 0>, <1 650 1000 0>,  /* HS G1 RB */

		<95 512 298189 0>, <1 650 1000 0>,  /* HS G2 RB */

		<95 512 596378 0>, <1 650 1000 0>,  /* HS G3 RB */

		<95 512 4096000 0>, <1 650 1000 0>; /* Max. bandwidth */

		<122 512 0 0>, <1 756 0 0>,          /* No vote */

		<122 512 922 0>, <1 756 1000 0>,     /* PWM G1 */

		<122 512 127796 0>, <1 756 1000 0>,  /* HS G1 RA */

		<122 512 255591 0>, <1 756 1000 0>,  /* HS G2 RA */

		<122 512 511181 0>, <1 756 1000 0>,  /* HS G3 RA */

		<122 512 149422 0>, <1 756 1000 0>,  /* HS G1 RB */

		<122 512 298189 0>, <1 756 1000 0>,  /* HS G2 RB */

		<122 512 596378 0>, <1 756 1000 0>,  /* HS G3 RB */

		<122 512 4096000 0>, <1 756 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

		"PWM_G1_L1",

		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",