Commit 965924ee authored Apr 12, 2018 by Mark Rutland Committed by Greg Kroah-Hartman Apr 20, 2018

arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro




From: Catalin Marinas <catalin.marinas@arm.com>

commit f33bcf03e6079668da6bf4eec4a7dcf9289131d0 upstream.

This patch takes the errata workaround code out of cpu_do_switch_mm into
a dedicated post_ttbr0_update_workaround macro which will be reused in a
subsequent patch.

Cc: Will Deacon <will.deacon@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Kees Cook <keescook@chromium.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com> [v4.9 backport]
Tested-by: Greg Hackmann <ghackmann@google.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent 6289541c

arch/arm64/include/asm/assembler.h

+14 −0

Original line number	Diff line number	Diff line
		@@ -434,4 +434,18 @@ alternative_endif
		.macro pte_to_phys, phys, pte
		and \phys, \pte, #(((1 << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
		.endm

		/*
		* Errata workaround post TTBR0_EL1 update.
		*/
		.macro post_ttbr0_update_workaround
		#ifdef CONFIG_CAVIUM_ERRATUM_27456
		alternative_if ARM64_WORKAROUND_CAVIUM_27456
		ic iallu
		dsb nsh
		isb
		alternative_else_nop_endif
		#endif
		.endm

		#endif /* __ASM_ASSEMBLER_H */

arch/arm64/mm/proc.S

+1 −5

Original line number	Diff line number	Diff line
		@@ -139,11 +139,7 @@ ENTRY(cpu_do_switch_mm)
		isb
		msr ttbr0_el1, x0 // now update TTBR0
		isb
		alternative_if ARM64_WORKAROUND_CAVIUM_27456
		ic iallu
		dsb nsh
		isb
		alternative_else_nop_endif
		post_ttbr0_update_workaround
		ret
		ENDPROC(cpu_do_switch_mm)