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Commit 9254bfa9 authored by Odelu Kukatla's avatar Odelu Kukatla
Browse files

ARM: dts: msm: Add support for clocks for SDM439/429 



CPU and GCC clock nodes are required by cpufreq and
other client drivers to be able to scale the frequencies.
Add the table of cpu clock frequencies supported.

Change-Id: Ic357039bc38c7c1f473cc1e33cb80fdaa6833b9b
Signed-off-by: default avatarOdelu Kukatla <okukatla@codeaurora.org>
parent 678382be

arch/arm64/boot/dts/qcom/sdm429.dtsi

+70 −0
Original line number Diff line number Diff line
@@ -108,3 +108,73 @@ 


	/delete-node/ cpuss0-step;

};



&clock_gcc {

	compatible = "qcom,gcc-sdm429";

	reg = <0x1800000 0x80000>,

		<0xb016000 0x00040>;

	reg-names = "cc_base", "apcs_c1_base";

	vdd_dig-supply = <&pm8953_s2_level>;

	vdd_hf_dig-supply = <&pm8953_s2_level_ao>;

	vdd_hf_pll-supply = <&pm8953_l7_ao>;

};



&clock_debug {

	compatible = "qcom,cc-debug-8917";

	reg = <0x1874000 0x4>,

		<0xb01101c 0x8>;

	reg-names = "cc_base", "meas";

	#clock-cells = <1>;

};



&soc {

	/delete-node/ qcom,cpu-clock-8939@b111050;

	clock_cpu: qcom,cpu-clock-8939@b111050 {

		compatible = "qcom,cpu-clock-sdm429";



		reg =   <0xb011050 0x8>,

			<0xb1d1050 0x8>,

			<0x00a412c 0x8>;

		reg-names = "apcs-c1-rcg-base",

			"apcs-cci-rcg-base", "efuse";



		qcom,num-cluster;

		vdd-c1-supply = <&apc_vreg_corner>;

		vdd-cci-supply = <&apc_vreg_corner>;



		clocks = <&clock_gcc clk_gpll0_ao_clk_src>,

			<&clock_gcc clk_a53ss_c1_pll>,

			<&clock_gcc clk_gpll0_ao_clk_src>,

			<&clock_gcc clk_gpll0_ao_clk_src>;

		clock-names = "clk-c1-4", "clk-c1-5",

				"clk-cci-4", "clk-cci-2";



		qcom,speed0-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1958400000 5>;



		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		qcom,speed1-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1804800000 5>;



		qcom,speed1-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;



		#clock-cells = <1>;

	};

};

arch/arm64/boot/dts/qcom/sdm439.dtsi

+61 −0
Original line number Diff line number Diff line
@@ -197,3 +197,64 @@ 
		memory-region = <&secure_mem>;

	};

};



&clock_cpu {

	compatible = "qcom,cpu-clock-sdm439";

	vdd-c0-supply = <&apc_vreg_corner>;

	vdd-c1-supply = <&apc_vreg_corner>;

	vdd-cci-supply = <&apc_vreg_corner>;

	qcom,speed0-bin-v0-c0 =

		<          0 0>,

		<  768000000 1>,

		<  998400000 1>,

		< 1171200000 2>,

		< 1305600000 3>,

		< 1459200000 5>;



	qcom,speed0-bin-v0-c1 =

		<          0 0>,

		< 1305600000 1>,

		< 1497600000 2>,

		< 1708800000 3>,

		< 1958400000 5>;



	qcom,speed0-bin-v0-cci =

		<          0 0>,

		<  400000000 1>,

		<  533333333 3>;



	qcom,speed1-bin-v0-c0 =

		<          0 0>,

		<  768000000 1>,

		<  998400000 1>,

		< 1171200000 2>,

		< 1305600000 3>,

		< 1459200000 5>;



	qcom,speed1-bin-v0-c1 =

		<          0 0>,

		< 1305600000 1>,

		< 1497600000 2>,

		< 1708800000 3>,

		< 1804800000 5>;



	qcom,speed1-bin-v0-cci =

		<          0 0>,

		<  400000000 1>,

		<  533333333 3>;

};



&clock_gcc {

	compatible = "qcom,gcc-sdm439";

	reg = <0x1800000 0x80000>,

		<0xb016000 0x00040>,

		<0xb116000 0x00040>,

		<0x00a6018 0x00004>;

	reg-names = "cc_base", "apcs_c1_base",

			"apcs_c0_base", "efuse";

	vdd_dig-supply = <&pm8953_s2_level>;

	vdd_sr2_dig-supply = <&pm8953_s2_level_ao>;

	vdd_sr2_pll-supply = <&pm8953_l7_ao>;

	vdd_hf_dig-supply = <&pm8953_s2_level_ao>;

	vdd_hf_pll-supply = <&pm8953_l7_ao>;

};