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Commit 8ee8ee52 authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru Committed by Gerrit - the friendly Code Review server
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drm: msm: dsi-staging: add support for DSI controller v2.0.0 



Add a separate DSI controller h/w driver to support DSI
controller v2.0.0. This includes reorganizing the DSI controller
programming sequence which is common between DSI v1.4.0 and
DSI v2.0.0 to a common DSI h/w driver file.

CRs-Fixed: 2008002
Change-Id: I6e2821b6874924c8fbaca888f940e8ad34ee90ec
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: default avatarShashank Babu Chinta Venkata <sbchin@codeaurora.org>
parent dbd2fb02

drivers/gpu/drm/msm/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -98,7 +98,9 @@ msm_drm-$(CONFIG_DRM_MSM_DSI_STAGING) += dsi-staging/dsi_phy.o \ 
				dsi-staging/dsi_pwr.o \

				dsi-staging/dsi_phy.o \

				dsi-staging/dsi_phy_hw_v4_0.o \

				dsi-staging/dsi_ctrl_hw_cmn.o \

				dsi-staging/dsi_ctrl_hw_1_4.o \

				dsi-staging/dsi_ctrl_hw_2_0.o \

				dsi-staging/dsi_ctrl.o \

				dsi-staging/dsi_catalog.o \

				dsi-staging/dsi_drm.o \

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c

+60 −44
Original line number Diff line number Diff line
@@ -18,56 +18,74 @@ 
#include "dsi_catalog.h"



/**

 * dsi_catalog_14_init() - catalog init for dsi controller v1.4

 * dsi_catalog_cmn_init() - catalog init for dsi controller v1.4

 */

static void dsi_catalog_14_init(struct dsi_ctrl_hw *ctrl)

static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl,

		enum dsi_ctrl_version version)

{

	ctrl->ops.host_setup             = dsi_ctrl_hw_14_host_setup;

	ctrl->ops.setup_lane_map         = dsi_ctrl_hw_14_setup_lane_map;

	ctrl->ops.video_engine_en        = dsi_ctrl_hw_14_video_engine_en;

	ctrl->ops.video_engine_setup     = dsi_ctrl_hw_14_video_engine_setup;

	ctrl->ops.set_video_timing       = dsi_ctrl_hw_14_set_video_timing;

	ctrl->ops.cmd_engine_setup       = dsi_ctrl_hw_14_cmd_engine_setup;

	ctrl->ops.setup_cmd_stream       = dsi_ctrl_hw_14_setup_cmd_stream;

	ctrl->ops.ctrl_en                = dsi_ctrl_hw_14_ctrl_en;

	ctrl->ops.cmd_engine_en          = dsi_ctrl_hw_14_cmd_engine_en;

	ctrl->ops.phy_sw_reset           = dsi_ctrl_hw_14_phy_sw_reset;

	ctrl->ops.soft_reset             = dsi_ctrl_hw_14_soft_reset;

	ctrl->ops.kickoff_command        = dsi_ctrl_hw_14_kickoff_command;

	ctrl->ops.kickoff_fifo_command   = dsi_ctrl_hw_14_kickoff_fifo_command;

	ctrl->ops.reset_cmd_fifo         = dsi_ctrl_hw_14_reset_cmd_fifo;

	ctrl->ops.trigger_command_dma    = dsi_ctrl_hw_14_trigger_command_dma;

	ctrl->ops.ulps_ops.ulps_request           = dsi_ctrl_hw_14_ulps_request;

	ctrl->ops.ulps_ops.ulps_exit     = dsi_ctrl_hw_14_ulps_exit;

	ctrl->ops.ulps_ops.wait_for_lane_idle = dsi_ctrl_hw_wait_for_lane_idle;

	ctrl->ops.ulps_ops.get_lanes_in_ulps = dsi_ctrl_hw_14_get_lanes_in_ulps;

	ctrl->ops.clamp_enable           = dsi_ctrl_hw_14_clamp_enable;

	ctrl->ops.clamp_disable          = dsi_ctrl_hw_14_clamp_disable;

	ctrl->ops.get_interrupt_status   = dsi_ctrl_hw_14_get_interrupt_status;

	ctrl->ops.get_error_status       = dsi_ctrl_hw_14_get_error_status;

	ctrl->ops.clear_error_status     = dsi_ctrl_hw_14_clear_error_status;

	/* common functions */

	ctrl->ops.host_setup             = dsi_ctrl_hw_cmn_host_setup;

	ctrl->ops.video_engine_en        = dsi_ctrl_hw_cmn_video_engine_en;

	ctrl->ops.video_engine_setup     = dsi_ctrl_hw_cmn_video_engine_setup;

	ctrl->ops.set_video_timing       = dsi_ctrl_hw_cmn_set_video_timing;

	ctrl->ops.cmd_engine_setup       = dsi_ctrl_hw_cmn_cmd_engine_setup;

	ctrl->ops.setup_cmd_stream       = dsi_ctrl_hw_cmn_setup_cmd_stream;

	ctrl->ops.ctrl_en                = dsi_ctrl_hw_cmn_ctrl_en;

	ctrl->ops.cmd_engine_en          = dsi_ctrl_hw_cmn_cmd_engine_en;

	ctrl->ops.phy_sw_reset           = dsi_ctrl_hw_cmn_phy_sw_reset;

	ctrl->ops.soft_reset             = dsi_ctrl_hw_cmn_soft_reset;

	ctrl->ops.kickoff_command        = dsi_ctrl_hw_cmn_kickoff_command;

	ctrl->ops.kickoff_fifo_command   = dsi_ctrl_hw_cmn_kickoff_fifo_command;

	ctrl->ops.reset_cmd_fifo         = dsi_ctrl_hw_cmn_reset_cmd_fifo;

	ctrl->ops.trigger_command_dma    = dsi_ctrl_hw_cmn_trigger_command_dma;

	ctrl->ops.get_interrupt_status   = dsi_ctrl_hw_cmn_get_interrupt_status;

	ctrl->ops.get_error_status       = dsi_ctrl_hw_cmn_get_error_status;

	ctrl->ops.clear_error_status     = dsi_ctrl_hw_cmn_clear_error_status;

	ctrl->ops.clear_interrupt_status =

		dsi_ctrl_hw_14_clear_interrupt_status;

		dsi_ctrl_hw_cmn_clear_interrupt_status;

	ctrl->ops.enable_status_interrupts =

		dsi_ctrl_hw_14_enable_status_interrupts;

		dsi_ctrl_hw_cmn_enable_status_interrupts;

	ctrl->ops.enable_error_interrupts =

		dsi_ctrl_hw_14_enable_error_interrupts;

		dsi_ctrl_hw_cmn_enable_error_interrupts;

	ctrl->ops.video_test_pattern_setup =

		dsi_ctrl_hw_14_video_test_pattern_setup;

		dsi_ctrl_hw_cmn_video_test_pattern_setup;

	ctrl->ops.cmd_test_pattern_setup =

		dsi_ctrl_hw_14_cmd_test_pattern_setup;

	ctrl->ops.test_pattern_enable    = dsi_ctrl_hw_14_test_pattern_enable;

		dsi_ctrl_hw_cmn_cmd_test_pattern_setup;

	ctrl->ops.test_pattern_enable    = dsi_ctrl_hw_cmn_test_pattern_enable;

	ctrl->ops.trigger_cmd_test_pattern =

		dsi_ctrl_hw_14_trigger_cmd_test_pattern;

	ctrl->ops.reg_dump_to_buffer    = dsi_ctrl_hw_14_reg_dump_to_buffer;

}

		dsi_ctrl_hw_cmn_trigger_cmd_test_pattern;

	ctrl->ops.clear_phy0_ln_err = dsi_ctrl_hw_dln0_phy_err;

	ctrl->ops.phy_reset_config = dsi_ctrl_hw_cmn_phy_reset_config;



/**

 * dsi_catalog_20_init() - catalog init for dsi controller v2.0

 */

static void dsi_catalog_20_init(struct dsi_ctrl_hw *ctrl)

{

	set_bit(DSI_CTRL_CPHY, ctrl->feature_map);

	switch (version) {

	case DSI_CTRL_VERSION_1_4:

		ctrl->ops.setup_lane_map = dsi_ctrl_hw_14_setup_lane_map;

		ctrl->ops.ulps_ops.ulps_request = dsi_ctrl_hw_14_ulps_request;

		ctrl->ops.ulps_ops.ulps_exit = dsi_ctrl_hw_14_ulps_exit;

		ctrl->ops.wait_for_lane_idle =

			dsi_ctrl_hw_14_wait_for_lane_idle;

		ctrl->ops.ulps_ops.get_lanes_in_ulps =

			dsi_ctrl_hw_14_get_lanes_in_ulps;

		ctrl->ops.clamp_enable = dsi_ctrl_hw_14_clamp_enable;

		ctrl->ops.clamp_disable = dsi_ctrl_hw_14_clamp_disable;

		ctrl->ops.reg_dump_to_buffer =

			dsi_ctrl_hw_14_reg_dump_to_buffer;

		break;

	case DSI_CTRL_VERSION_2_0:

		ctrl->ops.setup_lane_map = dsi_ctrl_hw_20_setup_lane_map;

		ctrl->ops.wait_for_lane_idle =

			dsi_ctrl_hw_20_wait_for_lane_idle;

		ctrl->ops.reg_dump_to_buffer =

			dsi_ctrl_hw_20_reg_dump_to_buffer;

		ctrl->ops.ulps_ops.ulps_request = NULL;

		ctrl->ops.ulps_ops.ulps_exit = NULL;

		ctrl->ops.ulps_ops.get_lanes_in_ulps = NULL;

		ctrl->ops.clamp_enable = NULL;

		ctrl->ops.clamp_disable = NULL;

		break;

	default:

		break;

	}

}



/**
@@ -102,10 +120,8 @@ int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl, 


	switch (version) {

	case DSI_CTRL_VERSION_1_4:

		dsi_catalog_14_init(ctrl);

		break;

	case DSI_CTRL_VERSION_2_0:

		dsi_catalog_20_init(ctrl);

		dsi_catalog_cmn_init(ctrl, version);

		break;

	default:

		return -ENOTSUPP;

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h

+53 −38
Original line number Diff line number Diff line
@@ -60,43 +60,69 @@ int dsi_phy_hw_v4_0_calculate_timing_params(struct dsi_phy_hw *phy, 
void dsi_phy_hw_v4_0_idle_on(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);

void dsi_phy_hw_v4_0_idle_off(struct dsi_phy_hw *phy);



/* Definitions for 1.4 controller hardware driver */

void dsi_ctrl_hw_14_host_setup(struct dsi_ctrl_hw *ctrl,

/* DSI controller common ops */

u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl);

void dsi_ctrl_hw_cmn_clear_interrupt_status(struct dsi_ctrl_hw *ctrl, u32 ints);

void dsi_ctrl_hw_cmn_enable_status_interrupts(struct dsi_ctrl_hw *ctrl,

					     u32 ints);



u64 dsi_ctrl_hw_cmn_get_error_status(struct dsi_ctrl_hw *ctrl);

void dsi_ctrl_hw_cmn_clear_error_status(struct dsi_ctrl_hw *ctrl, u64 errors);

void dsi_ctrl_hw_cmn_enable_error_interrupts(struct dsi_ctrl_hw *ctrl,

					    u64 errors);



void dsi_ctrl_hw_cmn_video_test_pattern_setup(struct dsi_ctrl_hw *ctrl,

				 enum dsi_test_pattern type,

				 u32 init_val);

void dsi_ctrl_hw_cmn_cmd_test_pattern_setup(struct dsi_ctrl_hw *ctrl,

			       enum dsi_test_pattern  type,

			       u32 init_val,

			       u32 stream_id);

void dsi_ctrl_hw_cmn_test_pattern_enable(struct dsi_ctrl_hw *ctrl, bool enable);

void dsi_ctrl_hw_cmn_trigger_cmd_test_pattern(struct dsi_ctrl_hw *ctrl,

				 u32 stream_id);



void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl,

			       struct dsi_host_common_cfg *config);

void dsi_ctrl_hw_14_video_engine_en(struct dsi_ctrl_hw *ctrl, bool on);

void dsi_ctrl_hw_14_video_engine_setup(struct dsi_ctrl_hw *ctrl,

void dsi_ctrl_hw_cmn_video_engine_en(struct dsi_ctrl_hw *ctrl, bool on);

void dsi_ctrl_hw_cmn_video_engine_setup(struct dsi_ctrl_hw *ctrl,

				       struct dsi_host_common_cfg *common_cfg,

				       struct dsi_video_engine_cfg *cfg);

void dsi_ctrl_hw_14_set_video_timing(struct dsi_ctrl_hw *ctrl,

void dsi_ctrl_hw_cmn_set_video_timing(struct dsi_ctrl_hw *ctrl,

			 struct dsi_mode_info *mode);



void dsi_ctrl_hw_14_cmd_engine_setup(struct dsi_ctrl_hw *ctrl,

void dsi_ctrl_hw_cmn_cmd_engine_setup(struct dsi_ctrl_hw *ctrl,

				     struct dsi_host_common_cfg *common_cfg,

				     struct dsi_cmd_engine_cfg *cfg);



void dsi_ctrl_hw_14_ctrl_en(struct dsi_ctrl_hw *ctrl, bool on);

void dsi_ctrl_hw_14_cmd_engine_en(struct dsi_ctrl_hw *ctrl, bool on);

void dsi_ctrl_hw_cmn_ctrl_en(struct dsi_ctrl_hw *ctrl, bool on);

void dsi_ctrl_hw_cmn_cmd_engine_en(struct dsi_ctrl_hw *ctrl, bool on);



void dsi_ctrl_hw_14_setup_cmd_stream(struct dsi_ctrl_hw *ctrl,

void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl,

				     u32 width_in_pixels,

				     u32 h_stride,

				     u32 height_in_lines,

				     u32 vc_id);

void dsi_ctrl_hw_14_phy_sw_reset(struct dsi_ctrl_hw *ctrl);

void dsi_ctrl_hw_14_soft_reset(struct dsi_ctrl_hw *ctrl);

void dsi_ctrl_hw_cmn_phy_sw_reset(struct dsi_ctrl_hw *ctrl);

void dsi_ctrl_hw_cmn_soft_reset(struct dsi_ctrl_hw *ctrl);



void dsi_ctrl_hw_14_setup_lane_map(struct dsi_ctrl_hw *ctrl,

		       struct dsi_lane_mapping *lane_map);

void dsi_ctrl_hw_14_kickoff_command(struct dsi_ctrl_hw *ctrl,

void dsi_ctrl_hw_cmn_kickoff_command(struct dsi_ctrl_hw *ctrl,

			struct dsi_ctrl_cmd_dma_info *cmd,

			u32 flags);



void dsi_ctrl_hw_14_kickoff_fifo_command(struct dsi_ctrl_hw *ctrl,

void dsi_ctrl_hw_cmn_kickoff_fifo_command(struct dsi_ctrl_hw *ctrl,

			     struct dsi_ctrl_cmd_dma_fifo_info *cmd,

			     u32 flags);

void dsi_ctrl_hw_14_reset_cmd_fifo(struct dsi_ctrl_hw *ctrl);

void dsi_ctrl_hw_14_trigger_command_dma(struct dsi_ctrl_hw *ctrl);

int dsi_ctrl_hw_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes);

void dsi_ctrl_hw_cmn_reset_cmd_fifo(struct dsi_ctrl_hw *ctrl);

void dsi_ctrl_hw_cmn_trigger_command_dma(struct dsi_ctrl_hw *ctrl);

void dsi_ctrl_hw_dln0_phy_err(struct dsi_ctrl_hw *ctrl);

void dsi_ctrl_hw_cmn_phy_reset_config(struct dsi_ctrl_hw *ctrl,

			bool enable);



/* Definitions specific to 1.4 DSI controller hardware */

int dsi_ctrl_hw_14_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes);

void dsi_ctrl_hw_14_setup_lane_map(struct dsi_ctrl_hw *ctrl,

		       struct dsi_lane_map *lane_map);

void dsi_ctrl_hw_14_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes);

void dsi_ctrl_hw_14_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes);

u32 dsi_ctrl_hw_14_get_lanes_in_ulps(struct dsi_ctrl_hw *ctrl);
@@ -108,27 +134,16 @@ void dsi_ctrl_hw_14_clamp_enable(struct dsi_ctrl_hw *ctrl, 
void dsi_ctrl_hw_14_clamp_disable(struct dsi_ctrl_hw *ctrl,

				  u32 lanes,

				  bool disable_ulps);

u32 dsi_ctrl_hw_14_get_interrupt_status(struct dsi_ctrl_hw *ctrl);

void dsi_ctrl_hw_14_clear_interrupt_status(struct dsi_ctrl_hw *ctrl, u32 ints);

void dsi_ctrl_hw_14_enable_status_interrupts(struct dsi_ctrl_hw *ctrl,

					     u32 ints);



u64 dsi_ctrl_hw_14_get_error_status(struct dsi_ctrl_hw *ctrl);

void dsi_ctrl_hw_14_clear_error_status(struct dsi_ctrl_hw *ctrl, u64 errors);

void dsi_ctrl_hw_14_enable_error_interrupts(struct dsi_ctrl_hw *ctrl,

					    u64 errors);



void dsi_ctrl_hw_14_video_test_pattern_setup(struct dsi_ctrl_hw *ctrl,

				 enum dsi_test_pattern type,

				 u32 init_val);

void dsi_ctrl_hw_14_cmd_test_pattern_setup(struct dsi_ctrl_hw *ctrl,

			       enum dsi_test_pattern  type,

			       u32 init_val,

			       u32 stream_id);

void dsi_ctrl_hw_14_test_pattern_enable(struct dsi_ctrl_hw *ctrl, bool enable);

void dsi_ctrl_hw_14_trigger_cmd_test_pattern(struct dsi_ctrl_hw *ctrl,

				 u32 stream_id);

ssize_t dsi_ctrl_hw_14_reg_dump_to_buffer(struct dsi_ctrl_hw *ctrl,

					  char *buf,

					  u32 size);



/* Definitions specific to 2.0 DSI controller hardware */

void dsi_ctrl_hw_20_setup_lane_map(struct dsi_ctrl_hw *ctrl,

		       struct dsi_lane_map *lane_map);

int dsi_ctrl_hw_20_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes);

ssize_t dsi_ctrl_hw_20_reg_dump_to_buffer(struct dsi_ctrl_hw *ctrl,

					  char *buf,

					  u32 size);



#endif /* _DSI_CATALOG_H_ */

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c

+44 −7
Original line number Diff line number Diff line
@@ -155,6 +155,7 @@ static ssize_t debugfs_reg_dump_read(struct file *file, 
		return rc;

	}



	if (dsi_ctrl->hw.ops.reg_dump_to_buffer)

	len = dsi_ctrl->hw.ops.reg_dump_to_buffer(&dsi_ctrl->hw,

		  buf, SZ_4K);
@@ -162,6 +163,7 @@ static ssize_t debugfs_reg_dump_read(struct file *file, 
	rc = dsi_ctrl->clk_cb.dsi_clk_cb(dsi_ctrl->clk_cb.priv, clk_info);

	if (rc) {

		pr_err("failed to disable DSI core clocks\n");

		kfree(buf);

		return rc;

	}
@@ -1007,12 +1009,18 @@ static int dsi_enable_ulps(struct dsi_ctrl *dsi_ctrl) 
	if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE)

		lanes = dsi_ctrl->host_config.common_config.data_lanes;



	rc = dsi_ctrl->hw.ops.ulps_ops.wait_for_lane_idle(&dsi_ctrl->hw, lanes);

	rc = dsi_ctrl->hw.ops.wait_for_lane_idle(&dsi_ctrl->hw, lanes);

	if (rc) {

		pr_err("lanes not entering idle, skip ULPS\n");

		return rc;

	}



	if (!dsi_ctrl->hw.ops.ulps_ops.ulps_request ||

			!dsi_ctrl->hw.ops.ulps_ops.ulps_exit) {

		pr_debug("DSI controller ULPS ops not present\n");

		return 0;

	}



	lanes |= DSI_CLOCK_LANE;

	dsi_ctrl->hw.ops.ulps_ops.ulps_request(&dsi_ctrl->hw, lanes);
@@ -1032,10 +1040,19 @@ static int dsi_disable_ulps(struct dsi_ctrl *dsi_ctrl) 
	int rc = 0;

	u32 ulps_lanes, lanes = 0;



	dsi_ctrl->hw.ops.clear_phy0_ln_err(&dsi_ctrl->hw);



	if (!dsi_ctrl->hw.ops.ulps_ops.ulps_request ||

			!dsi_ctrl->hw.ops.ulps_ops.ulps_exit) {

		pr_debug("DSI controller ULPS ops not present\n");

		return 0;

	}



	if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE)

		lanes = dsi_ctrl->host_config.common_config.data_lanes;



	lanes |= DSI_CLOCK_LANE;



	ulps_lanes = dsi_ctrl->hw.ops.ulps_ops.get_lanes_in_ulps(&dsi_ctrl->hw);



	if ((lanes & ulps_lanes) != lanes)
@@ -1565,6 +1582,26 @@ int dsi_ctrl_setup(struct dsi_ctrl *dsi_ctrl) 
	return rc;

}



/**

 * dsi_ctrl_phy_reset_config() - Mask/unmask propagation of ahb reset signal

 *	to DSI PHY hardware.

 * @dsi_ctrl:        DSI controller handle.

 * @enable:			Mask/unmask the PHY reset signal.

 *

 * Return: error code.

 */

int dsi_ctrl_phy_reset_config(struct dsi_ctrl *dsi_ctrl, bool enable)

{

	if (!dsi_ctrl) {

		pr_err("Invalid params\n");

		return -EINVAL;

	}



	if (dsi_ctrl->hw.ops.phy_reset_config)

		dsi_ctrl->hw.ops.phy_reset_config(&dsi_ctrl->hw, enable);



	return 0;

}



/**

 * dsi_ctrl_host_init() - Initialize DSI host hardware.
@@ -2089,12 +2126,6 @@ int dsi_ctrl_set_ulps(struct dsi_ctrl *dsi_ctrl, bool enable) 
		return -EINVAL;

	}



	if (!dsi_ctrl->hw.ops.ulps_ops.ulps_request ||

			!dsi_ctrl->hw.ops.ulps_ops.ulps_exit) {

		pr_debug("DSI controller ULPS ops not present\n");

		return 0;

	}



	mutex_lock(&dsi_ctrl->ctrl_lock);



	if (enable)
@@ -2133,6 +2164,12 @@ int dsi_ctrl_set_clamp_state(struct dsi_ctrl *dsi_ctrl, 
		return -EINVAL;

	}



	if (!dsi_ctrl->hw.ops.clamp_enable ||

			!dsi_ctrl->hw.ops.clamp_disable) {

		pr_debug("No clamp control for DSI controller\n");

		return 0;

	}



	mutex_lock(&dsi_ctrl->ctrl_lock);



	rc = dsi_enable_io_clamp(dsi_ctrl, enable, ulps_enabled);

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h

+10 −0
Original line number Diff line number Diff line
@@ -318,6 +318,16 @@ int dsi_ctrl_async_timing_update(struct dsi_ctrl *dsi_ctrl, 
 */

int dsi_ctrl_phy_sw_reset(struct dsi_ctrl *dsi_ctrl);



/**

 * dsi_ctrl_phy_reset_config() - Mask/unmask propagation of ahb reset signal

 *	to DSI PHY hardware.

 * @dsi_ctrl:        DSI controller handle.

 * @enable:			Mask/unmask the PHY reset signal.

 *

 * Return: error code.

 */

int dsi_ctrl_phy_reset_config(struct dsi_ctrl *dsi_ctrl, bool enable);



/**

 * dsi_ctrl_host_init() - Initialize DSI host hardware.

 * @dsi_ctrl:        DSI controller handle.