drm: msm: dsi-staging: add support for DSI clock manager (dbd2fb02) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/gpu/drm/msm/Makefile

+2 −1

Original line number	Diff line number	Diff line
		@@ -95,7 +95,7 @@ msm_drm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o
		msm_drm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/pll/dsi_pll_28nm_8960.o
		endif
		msm_drm-$(CONFIG_DRM_MSM_DSI_STAGING) += dsi-staging/dsi_phy.o \
		dsi-staging/dsi_clk_pwr.o \
		dsi-staging/dsi_pwr.o \
		dsi-staging/dsi_phy.o \
		dsi-staging/dsi_phy_hw_v4_0.o \
		dsi-staging/dsi_ctrl_hw_1_4.o \
		@@ -104,6 +104,7 @@ msm_drm-$(CONFIG_DRM_MSM_DSI_STAGING) += dsi-staging/dsi_phy.o \
		dsi-staging/dsi_drm.o \
		dsi-staging/dsi_display.o \
		dsi-staging/dsi_panel.o \
		dsi-staging/dsi_clk_manager.o \
		dsi-staging/dsi_display_test.o

		msm_drm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/pll/dsi_pll.o \

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c

+7 −5

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
		* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -37,10 +37,10 @@ static void dsi_catalog_14_init(struct dsi_ctrl_hw *ctrl)
		ctrl->ops.kickoff_fifo_command = dsi_ctrl_hw_14_kickoff_fifo_command;
		ctrl->ops.reset_cmd_fifo = dsi_ctrl_hw_14_reset_cmd_fifo;
		ctrl->ops.trigger_command_dma = dsi_ctrl_hw_14_trigger_command_dma;
		ctrl->ops.ulps_request = dsi_ctrl_hw_14_ulps_request;
		ctrl->ops.ulps_exit = dsi_ctrl_hw_14_ulps_exit;
		ctrl->ops.clear_ulps_request = dsi_ctrl_hw_14_clear_ulps_request;
		ctrl->ops.get_lanes_in_ulps = dsi_ctrl_hw_14_get_lanes_in_ulps;
		ctrl->ops.ulps_ops.ulps_request = dsi_ctrl_hw_14_ulps_request;
		ctrl->ops.ulps_ops.ulps_exit = dsi_ctrl_hw_14_ulps_exit;
		ctrl->ops.ulps_ops.wait_for_lane_idle = dsi_ctrl_hw_wait_for_lane_idle;
		ctrl->ops.ulps_ops.get_lanes_in_ulps = dsi_ctrl_hw_14_get_lanes_in_ulps;
		ctrl->ops.clamp_enable = dsi_ctrl_hw_14_clamp_enable;
		ctrl->ops.clamp_disable = dsi_ctrl_hw_14_clamp_disable;
		ctrl->ops.get_interrupt_status = dsi_ctrl_hw_14_get_interrupt_status;
		@@ -125,6 +125,8 @@ static void dsi_catalog_phy_4_0_init(struct dsi_phy_hw *phy)
		phy->ops.disable = dsi_phy_hw_v4_0_disable;
		phy->ops.calculate_timing_params =
		dsi_phy_hw_v4_0_calculate_timing_params;
		phy->ops.phy_idle_on = dsi_phy_hw_v4_0_idle_on;
		phy->ops.phy_idle_off = dsi_phy_hw_v4_0_idle_off;
		}

		/**

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h

+4 −3

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
		* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -57,6 +57,8 @@ int dsi_phy_hw_v4_0_calculate_timing_params(struct dsi_phy_hw *phy,
		struct dsi_host_common_cfg *cfg,
		struct dsi_phy_per_lane_cfgs
		*timing);
		void dsi_phy_hw_v4_0_idle_on(struct dsi_phy_hw phy, struct dsi_phy_cfg cfg);
		void dsi_phy_hw_v4_0_idle_off(struct dsi_phy_hw *phy);

		/* Definitions for 1.4 controller hardware driver */
		void dsi_ctrl_hw_14_host_setup(struct dsi_ctrl_hw *ctrl,
		@@ -94,10 +96,9 @@ void dsi_ctrl_hw_14_kickoff_fifo_command(struct dsi_ctrl_hw *ctrl,
		u32 flags);
		void dsi_ctrl_hw_14_reset_cmd_fifo(struct dsi_ctrl_hw *ctrl);
		void dsi_ctrl_hw_14_trigger_command_dma(struct dsi_ctrl_hw *ctrl);

		int dsi_ctrl_hw_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes);
		void dsi_ctrl_hw_14_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes);
		void dsi_ctrl_hw_14_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes);
		void dsi_ctrl_hw_14_clear_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes);
		u32 dsi_ctrl_hw_14_get_lanes_in_ulps(struct dsi_ctrl_hw *ctrl);

		void dsi_ctrl_hw_14_clamp_enable(struct dsi_ctrl_hw *ctrl,

drivers/gpu/drm/msm/dsi-staging/dsi_clk.h

0 → 100644

+249 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		*/

		#ifndef _DSI_CLK_H_
		#define _DSI_CLK_H_

		#include <linux/device.h>
		#include <linux/platform_device.h>
		#include <linux/types.h>
		#include <linux/clk.h>

		#define MAX_STRING_LEN 32
		#define MAX_DSI_CTRL 2

		enum dsi_clk_state {
		DSI_CLK_OFF,
		DSI_CLK_ON,
		DSI_CLK_EARLY_GATE,
		};

		enum clk_req_client {
		DSI_CLK_REQ_MDP_CLIENT = 0,
		DSI_CLK_REQ_DSI_CLIENT,
		};

		enum dsi_link_clk_type {
		DSI_LINK_ESC_CLK,
		DSI_LINK_BYTE_CLK,
		DSI_LINK_PIX_CLK,
		DSI_LINK_CLK_MAX,
		};

		enum dsi_clk_type {
		DSI_CORE_CLK = BIT(0),
		DSI_LINK_CLK = BIT(1),
		DSI_ALL_CLKS = (BIT(0) \| BIT(1)),
		DSI_CLKS_MAX = BIT(2),
		};

		struct dsi_clk_ctrl_info {
		enum dsi_clk_type clk_type;
		enum dsi_clk_state clk_state;
		enum clk_req_client client;
		};

		struct clk_ctrl_cb {
		void *priv;
		int (dsi_clk_cb)(void priv, struct dsi_clk_ctrl_info clk_ctrl_info);
		};

		/**
		* struct dsi_core_clk_info - Core clock information for DSI hardware
		* @mdp_core_clk: Handle to MDP core clock.
		* @iface_clk: Handle to MDP interface clock.
		* @core_mmss_clk: Handle to MMSS core clock.
		* @bus_clk: Handle to bus clock.
		*/
		struct dsi_core_clk_info {
		struct clk *mdp_core_clk;
		struct clk *iface_clk;
		struct clk *core_mmss_clk;
		struct clk *bus_clk;
		};

		/**
		* struct dsi_link_clk_info - Link clock information for DSI hardware.
		* @byte_clk: Handle to DSI byte clock.
		* @pixel_clk: Handle to DSI pixel clock.
		* @esc_clk: Handle to DSI escape clock.
		*/
		struct dsi_link_clk_info {
		struct clk *byte_clk;
		struct clk *pixel_clk;
		struct clk *esc_clk;
		};

		/**
		* struct link_clk_freq - Clock frequency information for Link clocks
		* @byte_clk_rate: Frequency of DSI byte clock in KHz.
		* @pixel_clk_rate: Frequency of DSI pixel clock in KHz.
		* @esc_clk_rate: Frequency of DSI escape clock in KHz.
		*/
		struct link_clk_freq {
		u32 byte_clk_rate;
		u32 pix_clk_rate;
		u32 esc_clk_rate;
		};

		/**
		* typedef *pre_clockoff_cb() - Callback before clock is turned off
		* @priv: private data pointer.
		* @clk_type: clock which is being turned off.
		* @new_state: next state for the clock.
		*
		* @return: error code.
		*/
		typedef int (pre_clockoff_cb)(void priv,
		enum dsi_clk_type clk_type,
		enum dsi_clk_state new_state);

		/**
		* typedef *post_clockoff_cb() - Callback after clock is turned off
		* @priv: private data pointer.
		* @clk_type: clock which was turned off.
		* @curr_state: current state for the clock.
		*
		* @return: error code.
		*/
		typedef int (post_clockoff_cb)(void priv,
		enum dsi_clk_type clk_type,
		enum dsi_clk_state curr_state);

		/**
		* typedef *post_clockon_cb() - Callback after clock is turned on
		* @priv: private data pointer.
		* @clk_type: clock which was turned on.
		* @curr_state: current state for the clock.
		*
		* @return: error code.
		*/
		typedef int (post_clockon_cb)(void priv,
		enum dsi_clk_type clk_type,
		enum dsi_clk_state curr_state);

		/**
		* typedef *pre_clockon_cb() - Callback before clock is turned on
		* @priv: private data pointer.
		* @clk_type: clock which is being turned on.
		* @new_state: next state for the clock.
		*
		* @return: error code.
		*/
		typedef int (pre_clockon_cb)(void priv,
		enum dsi_clk_type clk_type,
		enum dsi_clk_state new_state);


		struct dsi_clk_info {
		char name[MAX_STRING_LEN];
		struct dsi_core_clk_info c_clks[MAX_DSI_CTRL];
		struct dsi_link_clk_info l_clks[MAX_DSI_CTRL];
		u32 bus_handle[MAX_DSI_CTRL];
		pre_clockoff_cb pre_clkoff_cb;
		post_clockoff_cb post_clkoff_cb;
		post_clockon_cb post_clkon_cb;
		pre_clockon_cb pre_clkon_cb;
		void *priv_data;
		u32 master_ndx;
		u32 dsi_ctrl_count;
		};

		/**
		* struct dsi_clk_link_set - Pair of clock handles to describe link clocks
		* @byte_clk: Handle to DSi byte clock.
		* @pixel_clk: Handle to DSI pixel clock.
		*/
		struct dsi_clk_link_set {
		struct clk *byte_clk;
		struct clk *pixel_clk;
		};

		/**
		* dsi_display_clk_mgr_register() - Register DSI clock manager
		* @info: Structure containing DSI clock information
		*/
		void dsi_display_clk_mngr_register(struct dsi_clk_info info);

		/**
		* dsi_display_clk_mngr_deregister() - Deregister DSI clock manager
		* @clk_mngr: DSI clock manager pointer
		*/
		int dsi_display_clk_mngr_deregister(void *clk_mngr);

		/**
		* dsi_register_clk_handle() - Register clock handle with DSI clock manager
		* @clk_mngr: DSI clock manager pointer
		* @client: DSI clock client pointer.
		*/
		void dsi_register_clk_handle(void clk_mngr, char *client);

		/**
		* dsi_deregister_clk_handle() - Deregister clock handle from DSI clock manager
		* @client: DSI clock client pointer.
		*
		* return: error code in case of failure or 0 for success.
		*/
		int dsi_deregister_clk_handle(void *client);

		/**
		* dsi_display_clk_ctrl() - set frequencies for link clks
		* @handle: Handle of desired DSI clock client.
		* @clk_type: Clock which is being controlled.
		* @clk_state: Desired state of clock
		*
		* return: error code in case of failure or 0 for success.
		*/
		int dsi_display_clk_ctrl(void *handle,
		enum dsi_clk_type clk_type, enum dsi_clk_state clk_state);

		/**
		* dsi_clk_set_link_frequencies() - set frequencies for link clks
		* @client: DSI clock client pointer.
		* @freq: Structure containing link clock frequencies.
		* @index: Index of the DSI controller.
		*
		* return: error code in case of failure or 0 for success.
		*/
		int dsi_clk_set_link_frequencies(void *client, struct link_clk_freq freq,
		u32 index);


		/**
		* dsi_clk_set_pixel_clk_rate() - set frequency for pixel clock
		* @client: DSI clock client pointer.
		* @pixel_clk: Pixel clock rate in Hz.
		* @index: Index of the DSI controller.
		* return: error code in case of failure or 0 for success.
		*/
		int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index);


		/**
		* dsi_clk_set_byte_clk_rate() - set frequency for byte clock
		* @client: DSI clock client pointer.
		* @byte_clk: Pixel clock rate in Hz.
		* @index: Index of the DSI controller.
		* return: error code in case of failure or 0 for success.
		*/
		int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index);

		/**
		* dsi_clk_update_parent() - update parent clocks for specified clock
		* @parent: link clock pair which are set as parent.
		* @child: link clock pair whose parent has to be set.
		*/
		int dsi_clk_update_parent(struct dsi_clk_link_set *parent,
		struct dsi_clk_link_set *child);
		#endif /* _DSI_CLK_H_ */

drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c

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+1081 −0

File added.

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