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Commit 8bdaa32f authored by Harry Yang's avatar Harry Yang
Browse files

power: qpnp_smb2: configure to extend DRP.DFP time in try.SNK 



When both sides are doing DRP and the other side applies Rd near the end
of PMIC DFP cycle, sometimes, PMIC does not lock on into AttachedWait.SRC
and transitions back into Unattached.SNK.

If a resistance ranging (5.1k,300k) pulldown is applied and then 5.1kohms
pulldown is applied, then it takes 10-20ms to detect 5.1kohms.
Before this, if DRP.DFP time expires, then PMI transitions to UFP mode to
avoid extending DRP cycle time.

Fix it by extending DFP time. Note the total DRP time should still be
within max limit (100ms).

Change-Id: I1dd180229bc771542b4f6ca7850aa457478ae5cd
Signed-off-by: default avatarHarry Yang <harryy@codeaurora.org>
parent 739b514f

drivers/power/supply/qcom/qpnp-smb2.c

+12 −0
Original line number Diff line number Diff line
@@ -1664,6 +1664,18 @@ static int smb2_init_hw(struct smb2 *chip) 
		return rc;

	}



	/*

	 * allow DRP.DFP time to exceed by tPDdebounce time.

	 */

	rc = smblib_masked_write(chg, TAPER_TIMER_SEL_CFG_REG,

				TYPEC_DRP_DFP_TIME_CFG_BIT,

				TYPEC_DRP_DFP_TIME_CFG_BIT);

	if (rc < 0) {

		dev_err(chg->dev, "Couldn't configure DRP.DFP time rc=%d\n",

			rc);

		return rc;

	}



	/* configure float charger options */

	switch (chip->dt.float_option) {

	case 1:

drivers/power/supply/qcom/smb-reg.h

+1 −0
Original line number Diff line number Diff line
@@ -624,6 +624,7 @@ enum { 


#define TAPER_TIMER_SEL_CFG_REG			(USBIN_BASE + 0x64)

#define TYPEC_SPARE_CFG_BIT			BIT(7)

#define TYPEC_DRP_DFP_TIME_CFG_BIT		BIT(5)

#define TAPER_TIMER_SEL_MASK			GENMASK(1, 0)



#define USBIN_LOAD_CFG_REG			(USBIN_BASE + 0x65)