Loading drivers/media/platform/msm/sde/rotator/sde_rotator_base.h +2 −0 Original line number Diff line number Diff line Loading @@ -111,6 +111,7 @@ enum sde_rot_type { * @SDE_CAPS_R3_1P5_DOWNSCALE: 1.5x downscale rotator support * @SDE_CAPS_SBUF_1: stream buffer support for inline rotation * @SDE_CAPS_UBWC_2: universal bandwidth compression version 2 * @SDE_CAPS_PARTIALWR: partial write override */ enum sde_caps_settings { SDE_CAPS_R1_WB, Loading @@ -119,6 +120,7 @@ enum sde_caps_settings { SDE_CAPS_SEC_ATTACH_DETACH_SMMU, SDE_CAPS_SBUF_1, SDE_CAPS_UBWC_2, SDE_CAPS_PARTIALWR, SDE_CAPS_MAX, }; Loading drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c +8 −1 Original line number Diff line number Diff line Loading @@ -1264,6 +1264,7 @@ static void sde_hw_rotator_setup_wbengine(struct sde_hw_rotator_context *ctx, u32 *wrptr; u32 pack = 0; u32 dst_format = 0; u32 partial_write = 0; int i; wrptr = sde_hw_rotator_get_regdma_segment(ctx); Loading Loading @@ -1347,8 +1348,13 @@ static void sde_hw_rotator_setup_wbengine(struct sde_hw_rotator_context *ctx, cfg->v_downscale_factor | (cfg->h_downscale_factor << 16)); /* partial write check */ if (test_bit(SDE_CAPS_PARTIALWR, mdata->sde_caps_map) && !sde_mdp_is_ubwc_format(fmt)) partial_write = BIT(10); /* write config setup for bank configuration */ SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_WRITE_CONFIG, SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_WRITE_CONFIG, partial_write | (ctx->rot->highest_bank & 0x3) << 8); if (test_bit(SDE_CAPS_UBWC_2, mdata->sde_caps_map)) Loading Loading @@ -2589,6 +2595,7 @@ static int sde_rotator_hw_rev_init(struct sde_hw_rotator *rot) SDEROT_DBG("Supporting sys cache inline rotation\n"); set_bit(SDE_CAPS_SBUF_1, mdata->sde_caps_map); set_bit(SDE_CAPS_UBWC_2, mdata->sde_caps_map); set_bit(SDE_CAPS_PARTIALWR, mdata->sde_caps_map); rot->inpixfmts = sde_hw_rotator_v4_inpixfmts; rot->num_inpixfmt = ARRAY_SIZE(sde_hw_rotator_v4_inpixfmts); rot->outpixfmts = sde_hw_rotator_v4_outpixfmts; Loading Loading
drivers/media/platform/msm/sde/rotator/sde_rotator_base.h +2 −0 Original line number Diff line number Diff line Loading @@ -111,6 +111,7 @@ enum sde_rot_type { * @SDE_CAPS_R3_1P5_DOWNSCALE: 1.5x downscale rotator support * @SDE_CAPS_SBUF_1: stream buffer support for inline rotation * @SDE_CAPS_UBWC_2: universal bandwidth compression version 2 * @SDE_CAPS_PARTIALWR: partial write override */ enum sde_caps_settings { SDE_CAPS_R1_WB, Loading @@ -119,6 +120,7 @@ enum sde_caps_settings { SDE_CAPS_SEC_ATTACH_DETACH_SMMU, SDE_CAPS_SBUF_1, SDE_CAPS_UBWC_2, SDE_CAPS_PARTIALWR, SDE_CAPS_MAX, }; Loading
drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c +8 −1 Original line number Diff line number Diff line Loading @@ -1264,6 +1264,7 @@ static void sde_hw_rotator_setup_wbengine(struct sde_hw_rotator_context *ctx, u32 *wrptr; u32 pack = 0; u32 dst_format = 0; u32 partial_write = 0; int i; wrptr = sde_hw_rotator_get_regdma_segment(ctx); Loading Loading @@ -1347,8 +1348,13 @@ static void sde_hw_rotator_setup_wbengine(struct sde_hw_rotator_context *ctx, cfg->v_downscale_factor | (cfg->h_downscale_factor << 16)); /* partial write check */ if (test_bit(SDE_CAPS_PARTIALWR, mdata->sde_caps_map) && !sde_mdp_is_ubwc_format(fmt)) partial_write = BIT(10); /* write config setup for bank configuration */ SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_WRITE_CONFIG, SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_WRITE_CONFIG, partial_write | (ctx->rot->highest_bank & 0x3) << 8); if (test_bit(SDE_CAPS_UBWC_2, mdata->sde_caps_map)) Loading Loading @@ -2589,6 +2595,7 @@ static int sde_rotator_hw_rev_init(struct sde_hw_rotator *rot) SDEROT_DBG("Supporting sys cache inline rotation\n"); set_bit(SDE_CAPS_SBUF_1, mdata->sde_caps_map); set_bit(SDE_CAPS_UBWC_2, mdata->sde_caps_map); set_bit(SDE_CAPS_PARTIALWR, mdata->sde_caps_map); rot->inpixfmts = sde_hw_rotator_v4_inpixfmts; rot->num_inpixfmt = ARRAY_SIZE(sde_hw_rotator_v4_inpixfmts); rot->outpixfmts = sde_hw_rotator_v4_outpixfmts; Loading