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Commit 88b5198a authored by Taniya Das's avatar Taniya Das Committed by Padmanabhan Komanduru
Browse files

clk: qcom: Update the display port determine rate RCG ops 



The display port PLL generates only limited set of frequency combinations.
As fractional dividers are required to be used, update the RCG ops to
take care of the same.

Change-Id: I601273fee044ef128dbc7c2e23bc2d8ce10e31dc
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent c6d522c5

drivers/clk/qcom/clk-rcg2.c

+3 −10
Original line number Diff line number Diff line
@@ -1066,15 +1066,8 @@ static int clk_dp_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, 
static int clk_dp_determine_rate(struct clk_hw *hw,

		struct clk_rate_request *req)

{

	if (!hw)

		return -EINVAL;



	if (!clk_hw_get_parent(hw)) {

		pr_err("Missing the parent for the DP RCG\n");

		return -EINVAL;

	}



	req->best_parent_rate = clk_get_rate(clk_hw_get_parent(hw)->clk);

	req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw,

							req->best_parent_rate);

	return 0;

}