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Commit 877ec81d authored by Subhash Jadavani's avatar Subhash Jadavani Committed by Kyle Yan
Browse files

ARM: dts: msm: enable UFS and UFS PHY in msmskunk RUMI platform 



Enable UFS host controller and UFS PHY (attached to embedded UFS card)
for msmskunk RUMI platform.

Change-Id: I15e2e96ea1b73dc0a29ac4cfed4368c22d78cdb3
Signed-off-by: default avatarSubhash Jadavani <subhashj@codeaurora.org>
parent d6cf9e64

arch/arm64/boot/dts/qcom/msmskunk-rumi.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -9,3 +9,19 @@ 
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&ufsphy_mem {

	compatible = "qcom,ufs-phy-qrbtc-msmskunk";

	status = "ok";

};



&ufs_mem {

	lanes-per-direction = <1>;

	limit-tx-hs-gear = <1>;

	limit-rx-hs-gear = <1>;



	qcom,disable-lpm;

	rpm-level = <0>;

	spm-level = <0>;

	status = "ok";

};

arch/arm64/boot/dts/qcom/msmskunk.dtsi

+75 −0
Original line number Diff line number Diff line
@@ -320,6 +320,81 @@ 
		clock-output-names = "gpucc_clocks";

		#clock-cells = <1>;

	};



	ufsphy_mem: ufsphy@1d87000 {

		reg = <0x1d87000 0xda8>; /* PHY regs */

		reg-names = "phy_mem";

		#phy-cells = <0>;



		/* TODO: add "ref_clk_src" */

		clock-names = "ref_clk",

			"ref_aux_clk";

		clocks = <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,

			<&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;



		status = "disabled";

	};



	ufs_mem: ufshc@1d84000 {

		compatible = "qcom,ufshc";

		reg = <0x1d84000 0x2500>;

		interrupts = <0 265 0>;

		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";



		/* TODO: add "ref_clk" */

		clock-names =

			"core_clk",

			"bus_aggr_clk",

			"iface_clk",

			"core_clk_unipro",

			"core_clk_ice",

			"tx_lane0_sync_clk",

			"rx_lane0_sync_clk",

			"rx_lane1_sync_clk";

		clocks =

			<&clock_gcc GCC_UFS_PHY_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

			<&clock_gcc GCC_UFS_PHY_AHB_CLK>,

			<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

			<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,

			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

		freq-table-hz =

			<50000000 200000000>,

			<0 0>,

			<0 0>,

			<37500000 150000000>,

			<75000000 300000000>,

			<0 0>,

			<0 0>,

			<0 0>;



		qcom,msm-bus,name = "ufs_mem";

		qcom,msm-bus,num-cases = <12>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-KBps =

		<95 512 0 0>, <1 650 0 0>,          /* No vote */

		<95 512 922 0>, <1 650 1000 0>,     /* PWM G1 */

		<95 512 1844 0>, <1 650 1000 0>,    /* PWM G2 */

		<95 512 3688 0>, <1 650 1000 0>,    /* PWM G3 */

		<95 512 7376 0>, <1 650 1000 0>,    /* PWM G4 */

		<95 512 127796 0>, <1 650 1000 0>,  /* HS G1 RA */

		<95 512 255591 0>, <1 650 1000 0>,  /* HS G2 RA */

		<95 512 511181 0>, <1 650 1000 0>,  /* HS G3 RA */

		<95 512 149422 0>, <1 650 1000 0>,  /* HS G1 RB */

		<95 512 298189 0>, <1 650 1000 0>,  /* HS G2 RB */

		<95 512 596378 0>, <1 650 1000 0>,  /* HS G3 RB */

		<95 512 4096000 0>, <1 650 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",

		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",

		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",

		"MAX";



		status = "disabled";

	};

};



&pcie_0_gdsc {