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Commit d6cf9e64 authored by Subhash Jadavani's avatar Subhash Jadavani Committed by Kyle Yan
Browse files

phy: qcom-ufs-qrbtc-msmskunk: add phy support for msmskunk emulation 



This change adds support for UFS PHY supported on msmskunk emulation
platform.

Change-Id: I8d8d4dcc81d14c7c015ba0c38aa7b7c9fc085158
Signed-off-by: default avatarSubhash Jadavani <subhashj@codeaurora.org>
parent 5e45e706

Documentation/devicetree/bindings/ufs/ufs-qcom.txt

+7 −3
Original line number Diff line number Diff line
@@ -7,9 +7,13 @@ To bind UFS PHY with UFS host controller, the controller node should 
contain a phandle reference to UFS PHY node.



Required properties:

- compatible        : compatible list, contains "qcom,ufs-phy-qmp-20nm"

		      or "qcom,ufs-phy-qmp-14nm" or "qcom,ufs-phy-qmp-v3"

		      or "qcom,ufs-phy-qrbtc-v2" according to the relevant phy in use.

- compatible        : compatible list, contains one of the following:

		      "qcom,ufs-phy-qmp-20nm"

		      "qcom,ufs-phy-qmp-14nm"

		      "qcom,ufs-phy-qmp-v3"

		      "qcom,ufs-phy-qrbtc-v2"

		      "qcom,ufs-phy-qrbtc-msmskunk"

according to the relevant phy in use.

- reg               : should contain PHY register address space (mandatory),

- reg-names         : indicates various resources passed to driver (via reg proptery) by name.

                      Required "reg-names" is "phy_mem".

drivers/phy/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o 
obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-14nm.o

obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-v3.o

obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qrbtc-v2.o

obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qrbtc-msmskunk.o

obj-$(CONFIG_PHY_TUSB1210)		+= phy-tusb1210.o

obj-$(CONFIG_PHY_BRCM_SATA)		+= phy-brcm-sata.o

obj-$(CONFIG_PHY_PISTACHIO_USB)		+= phy-pistachio-usb.o

drivers/phy/phy-qcom-ufs-qrbtc-msmskunk.c

0 → 100644
+169 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016, Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */



#include "phy-qcom-ufs-qrbtc-msmskunk.h"



#define UFS_PHY_NAME "ufs_phy_qrbtc_msmskunk"



static

int ufs_qcom_phy_qrbtc_msmskunk_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,

					bool is_rate_B)

{

	int err;

	int tbl_size_A, tbl_size_B;

	struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;



	tbl_A = phy_cal_table_rate_A;

	tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);



	tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);

	tbl_B = phy_cal_table_rate_B;



	err = ufs_qcom_phy_calibrate(ufs_qcom_phy,

				     tbl_A, tbl_size_A,

				     tbl_B, tbl_size_B,

				     is_rate_B);



	if (err)

		dev_err(ufs_qcom_phy->dev,

			"%s: ufs_qcom_phy_calibrate() failed %d\n",

			__func__, err);



	return err;

}



static int

ufs_qcom_phy_qrbtc_msmskunk_is_pcs_ready(struct ufs_qcom_phy *phy_common)

{

	int err = 0;

	u32 val;



	/*

	 * The value we are polling for is 0x3D which represents the

	 * following masks:

	 * RESET_SM field: 0x5

	 * RESTRIMDONE bit: BIT(3)

	 * PLLLOCK bit: BIT(4)

	 * READY bit: BIT(5)

	 */

	#define QSERDES_COM_RESET_SM_REG_POLL_VAL	0x3D

	err = readl_poll_timeout(phy_common->mmio + QSERDES_COM_RESET_SM,

		val, (val == QSERDES_COM_RESET_SM_REG_POLL_VAL), 10, 1000000);



	if (err)

		dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",

			__func__, err);



	return err;

}



static void ufs_qcom_phy_qrbtc_msmskunk_start_serdes(struct ufs_qcom_phy *phy)

{

	u32 temp;



	writel_relaxed(0x01, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);



	temp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);

	temp |= 0x1;

	writel_relaxed(temp, phy->mmio + UFS_PHY_PHY_START);



	/* Ensure register value is committed */

	mb();

}



static int ufs_qcom_phy_qrbtc_msmskunk_init(struct phy *generic_phy)

{

	return 0;

}



struct phy_ops ufs_qcom_phy_qrbtc_msmskunk_phy_ops = {

	.init		= ufs_qcom_phy_qrbtc_msmskunk_init,

	.exit		= ufs_qcom_phy_exit,

	.owner		= THIS_MODULE,

};



struct ufs_qcom_phy_specific_ops phy_qrbtc_msmskunk_ops = {

	.calibrate_phy		= ufs_qcom_phy_qrbtc_msmskunk_phy_calibrate,

	.start_serdes		= ufs_qcom_phy_qrbtc_msmskunk_start_serdes,

	.is_physical_coding_sublayer_ready =

				ufs_qcom_phy_qrbtc_msmskunk_is_pcs_ready,

};



static int ufs_qcom_phy_qrbtc_msmskunk_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct phy *generic_phy;

	struct ufs_qcom_phy_qrbtc_msmskunk *phy;

	int err = 0;



	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);

	if (!phy) {

		err = -ENOMEM;

		goto out;

	}



	generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,

		&ufs_qcom_phy_qrbtc_msmskunk_phy_ops, &phy_qrbtc_msmskunk_ops);



	if (!generic_phy) {

		dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",

			__func__);

		err = -EIO;

		goto out;

	}



	phy_set_drvdata(generic_phy, phy);



	strlcpy(phy->common_cfg.name, UFS_PHY_NAME,

		sizeof(phy->common_cfg.name));



out:

	return err;

}



static int ufs_qcom_phy_qrbtc_msmskunk_remove(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct phy *generic_phy = to_phy(dev);

	struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);

	int err = 0;



	err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy);

	if (err)

		dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n",

			__func__, err);



	return err;

}



static const struct of_device_id ufs_qcom_phy_qrbtc_msmskunk_of_match[] = {

	{.compatible = "qcom,ufs-phy-qrbtc-msmskunk"},

	{},

};

MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qrbtc_msmskunk_of_match);



static struct platform_driver ufs_qcom_phy_qrbtc_msmskunk_driver = {

	.probe = ufs_qcom_phy_qrbtc_msmskunk_probe,

	.remove = ufs_qcom_phy_qrbtc_msmskunk_remove,

	.driver = {

		.of_match_table = ufs_qcom_phy_qrbtc_msmskunk_of_match,

		.name = "ufs_qcom_phy_qrbtc_msmskunk",

		.owner = THIS_MODULE,

	},

};



module_platform_driver(ufs_qcom_phy_qrbtc_msmskunk_driver);



MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QRBTC MSMSKUNK");

MODULE_LICENSE("GPL v2");

drivers/phy/phy-qcom-ufs-qrbtc-msmskunk.h

0 → 100644
+169 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016, Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */



#ifndef UFS_QCOM_PHY_QRBTC_MSMSKUNK_H_

#define UFS_QCOM_PHY_QRBTC_MSMSKUNK_H_



#include "phy-qcom-ufs-i.h"



/* QCOM UFS PHY control registers */

#define COM_OFF(x)	(0x000 + x)

#define TX_OFF(n, x)	(0x400 + (0x400 * n) + x)

#define RX_OFF(n, x)	(0x600 + (0x400 * n) + x)

#define PHY_OFF(x)	(0xC00 + x)

#define PHY_USR(x)	(x)



/* UFS PHY PLL block registers */

#define QSERDES_COM_SYS_CLK_CTRL		COM_OFF(0x00)

#define QSERDES_COM_PLL_VCOTAIL_EN		COM_OFF(0x04)

#define QSERDES_COM_PLL_CNTRL			COM_OFF(0x14)

#define QSERDES_COM_PLL_IP_SETI			COM_OFF(0x18)

#define	QSERDES_COM_BIAS_EN_CLKBUFLR_EN		COM_OFF(0x20)

#define QSERDES_COM_PLL_CP_SETI			COM_OFF(0x24)

#define QSERDES_COM_PLL_IP_SETP			COM_OFF(0x28)

#define QSERDES_COM_PLL_CP_SETP			COM_OFF(0x2C)

#define QSERDES_COM_SYSCLK_EN_SEL		COM_OFF(0x38)

#define QSERDES_COM_RES_CODE_TXBAND		COM_OFF(0x3C)

#define QSERDES_COM_RESETSM_CNTRL		COM_OFF(0x40)

#define QSERDES_COM_PLLLOCK_CMP1		COM_OFF(0x44)

#define QSERDES_COM_PLLLOCK_CMP2		COM_OFF(0x48)

#define QSERDES_COM_PLLLOCK_CMP3		COM_OFF(0x4C)

#define QSERDES_COM_PLLLOCK_CMP_EN		COM_OFF(0x50)

#define QSERDES_COM_DEC_START1			COM_OFF(0x64)

#define QSERDES_COM_DIV_FRAC_START1		COM_OFF(0x98)

#define QSERDES_COM_DIV_FRAC_START2		COM_OFF(0x9C)

#define QSERDES_COM_DIV_FRAC_START3		COM_OFF(0xA0)

#define QSERDES_COM_DEC_START2			COM_OFF(0xA4)

#define QSERDES_COM_PLL_RXTXEPCLK_EN		COM_OFF(0xA8)

#define QSERDES_COM_PLL_CRCTRL			COM_OFF(0xAC)

#define QSERDES_COM_PLL_CLKEPDIV		COM_OFF(0xB0)

#define QSERDES_COM_RESET_SM			COM_OFF(0xBC)



/* RX LANE n (0, 1) registers */

#define QSERDES_RX_CDR_CONTROL(n)		RX_OFF(n, 0x0)

#define QSERDES_RX_RX_IQ_RXDET_EN(n)		RX_OFF(n, 0x28)

#define QSERDES_RX_SIGDET_CNTRL(n)		RX_OFF(n, 0x34)

#define QSERDES_RX_RX_BAND(n)			RX_OFF(n, 0x38)

#define QSERDES_RX_CDR_CONTROL_HALF(n)		RX_OFF(n, 0x98)

#define QSERDES_RX_CDR_CONTROL_QUARTER(n)	RX_OFF(n, 0x9C)

#define QSERDES_RX_PWM_CNTRL1(n)		RX_OFF(n, 0x80)

#define QSERDES_RX_PWM_CNTRL2(n)		RX_OFF(n, 0x84)

#define QSERDES_RX_PWM_NDIV(n)			RX_OFF(n, 0x88)

#define QSERDES_RX_SIGDET_CNTRL2(n)		RX_OFF(n, 0x8C)

#define QSERDES_RX_UFS_CNTRL(n)			RX_OFF(n, 0x90)



/* UFS PHY registers */

#define UFS_PHY_PHY_START			PHY_OFF(0x00)

#define UFS_PHY_POWER_DOWN_CONTROL		PHY_OFF(0x04)

#define UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB	PHY_OFF(0x08)

#define UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB	PHY_OFF(0x0C)

#define UFS_PHY_RX_SYM_RESYNC_CTRL		PHY_OFF(0x134)



/* QRBTC V2 USER REGISTERS */

#define U11_UFS_RESET_REG_OFFSET		PHY_USR(0x4)

#define U11_QRBTC_CONTROL_OFFSET		PHY_USR(0x18)

#define U11_QRBTC_TX_CLK_CTRL			PHY_USR(0x20)



static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PHY_START, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x0F),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0x00),



	/* QSERDES Common */

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3F),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x16),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_TXBAND, 0xC0),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CNTRL, 0x24),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x10),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x13),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0x43),



	/* QSERDES RX0 */

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(0), 0x08),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL2(0), 0x40),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_NDIV(0), 0x30),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(0), 0x40),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0C),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(0), 0xC0),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(0), 0x07),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_BAND(0), 0x06),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(0), 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(0), 0xF3),



	/* QSERDES RX1 */

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL1(1), 0x08),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_CNTRL2(1), 0x40),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_PWM_NDIV(1), 0x30),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL(1), 0x40),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0C),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL(1), 0xC0),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL2(1), 0x07),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_BAND(1), 0x06),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UFS_CNTRL(1), 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_IQ_RXDET_EN(1), 0xF3),



	/* QSERDES PLL Settings - Series A */

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x10),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xFF),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x07),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x0F),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x07),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x01),

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {

	/* QSERDES PLL Settings - Series B */

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x10),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1E),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x07),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x0F),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x07),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x01),

};





/*

 * This structure represents the qrbtc-msmskunk specific phy.

 * common_cfg MUST remain the first field in this structure

 * in case extra fields are added. This way, when calling

 * get_ufs_qcom_phy() of generic phy, we can extract the

 * common phy structure (struct ufs_qcom_phy) out of it

 * regardless of the relevant specific phy.

 */

struct ufs_qcom_phy_qrbtc_msmskunk {

	struct ufs_qcom_phy common_cfg;

};



#endif