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Commit 823066d9 authored by Andre Przywara's avatar Andre Przywara Committed by Catalin Marinas
Browse files

arm64: include alternative handling in dcache_by_line_op 



The newly introduced dcache_by_line_op macro is used at least in
one occassion at the moment to issue a "dc cvau" instruction,
which is affected by ARM errata 819472, 826319, 827319 and 824069.
Change the macro to allow for alternative patching in there to
protect affected Cortex-A53 cores.

Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
[catalin.marinas@arm.com: indentation fixups]
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 290622ef

arch/arm64/include/asm/assembler.h

+11 −1
Original line number Original line Diff line number Diff line
@@ -24,6 +24,7 @@ 
#define __ASM_ASSEMBLER_H

#define __ASM_ASSEMBLER_H





#include <asm/asm-offsets.h>

#include <asm/asm-offsets.h>

#include <asm/cpufeature.h>

#include <asm/page.h>

#include <asm/page.h>

#include <asm/pgtable-hwdef.h>

#include <asm/pgtable-hwdef.h>

#include <asm/ptrace.h>

#include <asm/ptrace.h>
@@ -261,7 +262,16 @@ lr .req x30 // link register 
	add	\size, \kaddr, \size

	add	\size, \kaddr, \size

	sub	\tmp2, \tmp1, #1

	sub	\tmp2, \tmp1, #1

	bic	\kaddr, \kaddr, \tmp2

	bic	\kaddr, \kaddr, \tmp2

9998:	dc	\op, \kaddr

9998:

	.if	(\op == cvau || \op == cvac)

alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE

	dc	\op, \kaddr

alternative_else

	dc	civac, \kaddr

alternative_endif

	.else

	dc	\op, \kaddr

	.endif

	add	\kaddr, \kaddr, \tmp1

	add	\kaddr, \kaddr, \tmp1

	cmp	\kaddr, \size

	cmp	\kaddr, \size

	b.lo	9998b

	b.lo	9998b