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Commit 290622ef authored by Andre Przywara's avatar Andre Przywara Committed by Catalin Marinas
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arm64: fix "dc cvau" cache operation on errata-affected core 



The ARM errata 819472, 826319, 827319 and 824069 for affected
Cortex-A53 cores demand to promote "dc cvau" instructions to
"dc civac" as well.
Attribute the usage of the instruction in __flush_cache_user_range
to also be covered by our alternative patching efforts.
For that we introduce an assembly macro which both deals with
alternatives while still tagging the instructions as USER.

Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent b82bfa47

arch/arm64/include/asm/alternative.h

+4 −0
Original line number Diff line number Diff line
@@ -133,6 +133,10 @@ void apply_alternatives(void *start, size_t length); 
#define _ALTERNATIVE_CFG(insn1, insn2, cap, cfg, ...)	\

	alternative_insn insn1, insn2, cap, IS_ENABLED(cfg)



.macro user_alt, label, oldinstr, newinstr, cond

9999:	alternative_insn "\oldinstr", "\newinstr", \cond

	_ASM_EXTABLE 9999b, \label

.endm



/*

 * Generate the assembly for UAO alternatives with exception table entries.

arch/arm64/mm/cache.S

+1 −1
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ ENTRY(__flush_cache_user_range) 
	sub	x3, x2, #1

	bic	x4, x0, x3

1:

USER(9f, dc	cvau, x4	)		// clean D line to PoU

user_alt 9f, "dc cvau, x4",  "dc civac, x4",  ARM64_WORKAROUND_CLEAN_CACHE

	add	x4, x4, x2

	cmp	x4, x1

	b.lo	1b