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Commit 7d9eee6e authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Octeon: Make MSI use handle_simple_irq(). 



The use of handle_percpu_irq() is not really what we want for MSI, use
handle_simple_irq() instead.  This is probably the prototypical case
for using handle_simple_irq(), because all the MSIs are dispatched from
the root interrupt service routine.

Also since the base IRQ is not shared, don't pass IRQF_SHARED.

Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1488/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent a5decf70

arch/mips/pci/msi-octeon.c

+15 −46
Original line number Diff line number Diff line
@@ -228,22 +228,20 @@ static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id) 
	irq = fls64(msi_bits);

	if (irq) {

		irq += OCTEON_IRQ_MSI_BIT0 - 1;

		if (irq_desc[irq].action) {

			do_IRQ(irq);

			return IRQ_HANDLED;

		} else {

			pr_err("Spurious MSI interrupt %d\n", irq);

		if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {

			/* These chips have PCIe */

			cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,

					       1ull << (irq -

							OCTEON_IRQ_MSI_BIT0));

				       1ull << (irq - OCTEON_IRQ_MSI_BIT0));

		} else {

			/* These chips have PCI */

			cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,

					       1ull << (irq -

							OCTEON_IRQ_MSI_BIT0));

				       1ull << (irq - OCTEON_IRQ_MSI_BIT0));

		}

		if (irq_desc[irq].action) {

			do_IRQ(irq);

			return IRQ_HANDLED;

		} else {

			pr_err("Spurious MSI interrupt %d\n", irq);

		}

	}

	return IRQ_NONE;
@@ -251,27 +249,6 @@ static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id) 


static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);



static void octeon_irq_msi_ack(unsigned int irq)

{

	if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {

		/* These chips have PCI */

		cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,

			       1ull << (irq - OCTEON_IRQ_MSI_BIT0));

	} else {

		/*

		 * These chips have PCIe. Thankfully the ACK doesn't

		 * need any locking.

		 */

		cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,

			       1ull << (irq - OCTEON_IRQ_MSI_BIT0));

	}

}



static void octeon_irq_msi_eoi(unsigned int irq)

{

	/* Nothing needed */

}



static void octeon_irq_msi_enable(unsigned int irq)

{

	if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
@@ -326,8 +303,6 @@ static struct irq_chip octeon_irq_chip_msi = { 
	.name = "MSI",

	.enable = octeon_irq_msi_enable,

	.disable = octeon_irq_msi_disable,

	.ack = octeon_irq_msi_ack,

	.eoi = octeon_irq_msi_eoi,

};



/*
@@ -338,34 +313,28 @@ static int __init octeon_msi_initialize(void) 
	int irq;



	for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++) {

		set_irq_chip_and_handler(irq, &octeon_irq_chip_msi,

					 handle_percpu_irq);

		set_irq_chip_and_handler(irq, &octeon_irq_chip_msi, handle_simple_irq);

	}



	if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {

		if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,

				IRQF_SHARED,

				"MSI[0:63]", octeon_msi_interrupt))

				0, "MSI[0:63]", octeon_msi_interrupt))

			panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");

	} else if (octeon_is_pci_host()) {

		if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,

				IRQF_SHARED,

				"MSI[0:15]", octeon_msi_interrupt))

				0, "MSI[0:15]", octeon_msi_interrupt))

			panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");



		if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,

				IRQF_SHARED,

				"MSI[16:31]", octeon_msi_interrupt))

				0, "MSI[16:31]", octeon_msi_interrupt))

			panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");



		if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,

				IRQF_SHARED,

				"MSI[32:47]", octeon_msi_interrupt))

				0, "MSI[32:47]", octeon_msi_interrupt))

			panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");



		if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,

				IRQF_SHARED,

				"MSI[48:63]", octeon_msi_interrupt))

				0, "MSI[48:63]", octeon_msi_interrupt))

			panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");



	}