drm/msm/dsi-staging: fix dsi underflow errors during clock switch

Currently in dsi driver, for command mode panels the dsi bit clock
can be changed via sysfs node. This creates a race condition where
at the same time sysfs update was triggered and a commit was triggered
to come out of idle screen. When this scenario occurs then dsi might
go into bad state and throw FIFO errors, if one of the dsi clock got
enabled with old rate as part of the commit and the other dsi clock
got enabled with new rate triggered from sysfs node. Fix this race
condition by making clock update and sysfs node write mutually exclusive.

Change-Id: I7c361ccccc9ce7bdac8d46ecb892ae5f5c7c98e2
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>