Loading drivers/video/fbdev/msm/mdss.h +1 −0 Original line number Diff line number Diff line Loading @@ -42,6 +42,7 @@ enum mdss_mdp_clk_type { MDSS_CLK_MDP_CORE, MDSS_CLK_MDP_LUT, MDSS_CLK_MDP_VSYNC, MDSS_CLK_MNOC_AHB, MDSS_MAX_CLK }; Loading drivers/video/fbdev/msm/mdss_mdp.c +6 −0 Original line number Diff line number Diff line Loading @@ -1270,6 +1270,7 @@ static inline void __mdss_mdp_reg_access_clk_enable( mdss_update_reg_bus_vote(mdata->reg_bus_clt, VOTE_INDEX_LOW); mdss_bus_rt_bw_vote(true); mdss_mdp_clk_update(MDSS_CLK_MNOC_AHB, 1); mdss_mdp_clk_update(MDSS_CLK_AHB, 1); mdss_mdp_clk_update(MDSS_CLK_AXI, 1); mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, 1); Loading @@ -1278,6 +1279,7 @@ static inline void __mdss_mdp_reg_access_clk_enable( mdss_mdp_clk_update(MDSS_CLK_AXI, 0); mdss_mdp_clk_update(MDSS_CLK_AHB, 0); mdss_bus_rt_bw_vote(false); mdss_mdp_clk_update(MDSS_CLK_MNOC_AHB, 0); mdss_update_reg_bus_vote(mdata->reg_bus_clt, VOTE_INDEX_DISABLE); } Loading Loading @@ -1558,6 +1560,7 @@ void mdss_mdp_clk_ctrl(int enable) mdata->clk_ena = enable; spin_unlock_irqrestore(&mdp_lock, flags); mdss_mdp_clk_update(MDSS_CLK_MNOC_AHB, enable); mdss_mdp_clk_update(MDSS_CLK_AHB, enable); mdss_mdp_clk_update(MDSS_CLK_AXI, enable); mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, enable); Loading Loading @@ -1721,6 +1724,9 @@ static int mdss_mdp_irq_clk_setup(struct mdss_data_type *mdata) /* vsync_clk is optional for non-smart panels */ mdss_mdp_irq_clk_register(mdata, "vsync_clk", MDSS_CLK_MDP_VSYNC); /* this clk is not present on all MDSS revisions */ mdss_mdp_irq_clk_register(mdata, "mnoc_clk", MDSS_CLK_MNOC_AHB); /* Setting the default clock rate to the max supported.*/ mdss_mdp_set_clk_rate(mdata->max_mdp_clk_rate); pr_debug("mdp clk rate=%ld\n", Loading drivers/video/fbdev/msm/mdss_mdp_util.c +3 −2 Original line number Diff line number Diff line Loading @@ -31,6 +31,7 @@ #include "mdss_panel.h" #define PHY_ADDR_4G (1ULL<<32) #define ALIGN_UP(x, align) ((DIV_ROUND_UP((x), (align))) * (align)) void mdss_mdp_format_flag_removal(u32 *table, u32 num, u32 remove_bits) { Loading Loading @@ -451,13 +452,13 @@ static int mdss_mdp_get_ubwc_plane_size(struct mdss_mdp_format_params *fmt, } /* Y bitstream stride and plane size */ ps->ystride[0] = ALIGN(width, y_stride_alignment); ps->ystride[0] = ALIGN_UP(width, y_stride_alignment); ps->ystride[0] = (ps->ystride[0] * y_bpp_numer) / y_bpp_denom; ps->plane_size[0] = ALIGN(ps->ystride[0] * ALIGN(height, y_height_alignment), 4096); /* CbCr bitstream stride and plane size */ ps->ystride[1] = ALIGN(width / 2, uv_stride_alignment); ps->ystride[1] = ALIGN_UP(width / 2, uv_stride_alignment); ps->ystride[1] = (ps->ystride[1] * uv_bpp_numer) / uv_bpp_denom; ps->plane_size[1] = ALIGN(ps->ystride[1] * ALIGN(height / 2, uv_height_alignment), 4096); Loading Loading
drivers/video/fbdev/msm/mdss.h +1 −0 Original line number Diff line number Diff line Loading @@ -42,6 +42,7 @@ enum mdss_mdp_clk_type { MDSS_CLK_MDP_CORE, MDSS_CLK_MDP_LUT, MDSS_CLK_MDP_VSYNC, MDSS_CLK_MNOC_AHB, MDSS_MAX_CLK }; Loading
drivers/video/fbdev/msm/mdss_mdp.c +6 −0 Original line number Diff line number Diff line Loading @@ -1270,6 +1270,7 @@ static inline void __mdss_mdp_reg_access_clk_enable( mdss_update_reg_bus_vote(mdata->reg_bus_clt, VOTE_INDEX_LOW); mdss_bus_rt_bw_vote(true); mdss_mdp_clk_update(MDSS_CLK_MNOC_AHB, 1); mdss_mdp_clk_update(MDSS_CLK_AHB, 1); mdss_mdp_clk_update(MDSS_CLK_AXI, 1); mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, 1); Loading @@ -1278,6 +1279,7 @@ static inline void __mdss_mdp_reg_access_clk_enable( mdss_mdp_clk_update(MDSS_CLK_AXI, 0); mdss_mdp_clk_update(MDSS_CLK_AHB, 0); mdss_bus_rt_bw_vote(false); mdss_mdp_clk_update(MDSS_CLK_MNOC_AHB, 0); mdss_update_reg_bus_vote(mdata->reg_bus_clt, VOTE_INDEX_DISABLE); } Loading Loading @@ -1558,6 +1560,7 @@ void mdss_mdp_clk_ctrl(int enable) mdata->clk_ena = enable; spin_unlock_irqrestore(&mdp_lock, flags); mdss_mdp_clk_update(MDSS_CLK_MNOC_AHB, enable); mdss_mdp_clk_update(MDSS_CLK_AHB, enable); mdss_mdp_clk_update(MDSS_CLK_AXI, enable); mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, enable); Loading Loading @@ -1721,6 +1724,9 @@ static int mdss_mdp_irq_clk_setup(struct mdss_data_type *mdata) /* vsync_clk is optional for non-smart panels */ mdss_mdp_irq_clk_register(mdata, "vsync_clk", MDSS_CLK_MDP_VSYNC); /* this clk is not present on all MDSS revisions */ mdss_mdp_irq_clk_register(mdata, "mnoc_clk", MDSS_CLK_MNOC_AHB); /* Setting the default clock rate to the max supported.*/ mdss_mdp_set_clk_rate(mdata->max_mdp_clk_rate); pr_debug("mdp clk rate=%ld\n", Loading
drivers/video/fbdev/msm/mdss_mdp_util.c +3 −2 Original line number Diff line number Diff line Loading @@ -31,6 +31,7 @@ #include "mdss_panel.h" #define PHY_ADDR_4G (1ULL<<32) #define ALIGN_UP(x, align) ((DIV_ROUND_UP((x), (align))) * (align)) void mdss_mdp_format_flag_removal(u32 *table, u32 num, u32 remove_bits) { Loading Loading @@ -451,13 +452,13 @@ static int mdss_mdp_get_ubwc_plane_size(struct mdss_mdp_format_params *fmt, } /* Y bitstream stride and plane size */ ps->ystride[0] = ALIGN(width, y_stride_alignment); ps->ystride[0] = ALIGN_UP(width, y_stride_alignment); ps->ystride[0] = (ps->ystride[0] * y_bpp_numer) / y_bpp_denom; ps->plane_size[0] = ALIGN(ps->ystride[0] * ALIGN(height, y_height_alignment), 4096); /* CbCr bitstream stride and plane size */ ps->ystride[1] = ALIGN(width / 2, uv_stride_alignment); ps->ystride[1] = ALIGN_UP(width / 2, uv_stride_alignment); ps->ystride[1] = (ps->ystride[1] * uv_bpp_numer) / uv_bpp_denom; ps->plane_size[1] = ALIGN(ps->ystride[1] * ALIGN(height / 2, uv_height_alignment), 4096); Loading