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Commit 6d68a7b4 authored by Abhijit Kulkarni's avatar Abhijit Kulkarni Committed by Animesh Kishore
Browse files

msm: mdss: enable additonal clocks 



Need to enable clk_mmss_mnoc_ahb_clk before turning on the ahb_clk,
as there is a core fsm dependency between these clocks.

CRs-Fixed: 1008505
Change-Id: I9c87fee27c6a6ef875100c9fc1b9d0cb7c14a2b5
Signed-off-by: default avatarAbhijit Kulkarni <kabhijit@codeaurora.org>
parent 6106fc7b

drivers/video/fbdev/msm/mdss.h

+1 −0
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ enum mdss_mdp_clk_type { 
	MDSS_CLK_MDP_CORE,

	MDSS_CLK_MDP_LUT,

	MDSS_CLK_MDP_VSYNC,

	MDSS_CLK_MNOC_AHB,

	MDSS_MAX_CLK

};

drivers/video/fbdev/msm/mdss_mdp.c

+6 −0
Original line number Diff line number Diff line
@@ -1270,6 +1270,7 @@ static inline void __mdss_mdp_reg_access_clk_enable( 
		mdss_update_reg_bus_vote(mdata->reg_bus_clt,

				VOTE_INDEX_LOW);

		mdss_bus_rt_bw_vote(true);

		mdss_mdp_clk_update(MDSS_CLK_MNOC_AHB, 1);

		mdss_mdp_clk_update(MDSS_CLK_AHB, 1);

		mdss_mdp_clk_update(MDSS_CLK_AXI, 1);

		mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, 1);
@@ -1278,6 +1279,7 @@ static inline void __mdss_mdp_reg_access_clk_enable( 
		mdss_mdp_clk_update(MDSS_CLK_AXI, 0);

		mdss_mdp_clk_update(MDSS_CLK_AHB, 0);

		mdss_bus_rt_bw_vote(false);

		mdss_mdp_clk_update(MDSS_CLK_MNOC_AHB, 0);

		mdss_update_reg_bus_vote(mdata->reg_bus_clt,

				VOTE_INDEX_DISABLE);

	}
@@ -1558,6 +1560,7 @@ void mdss_mdp_clk_ctrl(int enable) 
		mdata->clk_ena = enable;

		spin_unlock_irqrestore(&mdp_lock, flags);



		mdss_mdp_clk_update(MDSS_CLK_MNOC_AHB, enable);

		mdss_mdp_clk_update(MDSS_CLK_AHB, enable);

		mdss_mdp_clk_update(MDSS_CLK_AXI, enable);

		mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, enable);
@@ -1721,6 +1724,9 @@ static int mdss_mdp_irq_clk_setup(struct mdss_data_type *mdata) 
	/* vsync_clk is optional for non-smart panels */

	mdss_mdp_irq_clk_register(mdata, "vsync_clk", MDSS_CLK_MDP_VSYNC);



	/* this clk is not present on all MDSS revisions */

	mdss_mdp_irq_clk_register(mdata, "mnoc_clk", MDSS_CLK_MNOC_AHB);



	/* Setting the default clock rate to the max supported.*/

	mdss_mdp_set_clk_rate(mdata->max_mdp_clk_rate);

	pr_debug("mdp clk rate=%ld\n",