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Commit 7879c157 authored by Kuogee Hsieh's avatar Kuogee Hsieh Committed by Narendra Muppalla
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msm: mdss: fixed calculation of pll fractional divider 



Pll unlocked due to wrong pll fractional divider calculated.
Pll fraction divider should be reminder of 2^20 after vco
rate divided by reference clock rate.

Change-Id: I9e4c2e3c0631e533d114c3e6acf65b71b9bf00d2
Signed-off-by: default avatarKuogee Hsieh <khsieh@codeaurora.org>
parent bfbfa0d2

drivers/clk/qcom/mdss/mdss-dsi-pll-8996-util.c

+3 −3
Original line number Diff line number Diff line
@@ -347,7 +347,7 @@ static void pll_8996_dec_frac_calc(struct dsi_pll_db *pdb, 
				vco_clk_rate, fref);



	dec_start_multiple = div_s64(vco_clk_rate * multiplier, fref);

	div_s64_rem(vco_clk_rate * multiplier, fref, &div_frac_start);

	div_s64_rem(dec_start_multiple, multiplier, &div_frac_start);



	dec_start = div_s64(dec_start_multiple, multiplier);
@@ -534,7 +534,7 @@ static void pll_db_commit_8996(void __iomem *pll_base, 
	data &= 0x0ff;

	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_DIV_FRAC_START2, data);

	data = (pout->div_frac_start >> 16);

	data &= 0x0ff;

	data &= 0x0f;

	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_DIV_FRAC_START3, data);



	data = pout->plllock_cmp;
@@ -651,7 +651,7 @@ unsigned long pll_vco_get_rate_8996(struct clk *c) 
	pr_debug("dec_start = 0x%x\n", dec_start);



	div_frac_start = (MDSS_PLL_REG_R(pll->pll_base,

			DSIPHY_PLL_DIV_FRAC_START3) & 0x0ff) << 16;

			DSIPHY_PLL_DIV_FRAC_START3) & 0x0f) << 16;

	div_frac_start |= (MDSS_PLL_REG_R(pll->pll_base,

			DSIPHY_PLL_DIV_FRAC_START2) & 0x0ff) << 8;

	div_frac_start |= MDSS_PLL_REG_R(pll->pll_base,