clk: mdss: Remove pll support for all targets except msm8996 (bfbfa0d2) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/clk/qcom/mdss/Makefile

+0 −7

Original line number	Original line	Diff line number	Diff line
	obj-$(CONFIG_MSM_MDSS_PLL) += mdss-pll-util.o		obj-$(CONFIG_MSM_MDSS_PLL) += mdss-pll-util.o
	obj-$(CONFIG_MSM_MDSS_PLL) += mdss-pll.o		obj-$(CONFIG_MSM_MDSS_PLL) += mdss-pll.o
	obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-util.o mdss-dsi-20nm-pll-util.o
	obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-28hpm.o
	obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-28lpm.o
	obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-20nm.o
	obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996.o		obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996.o
	obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996-util.o		obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996-util.o
	obj-$(CONFIG_MSM_MDSS_PLL) += mdss-edp-pll-28hpm.o
	obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-28hpm.o
	obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-20nm.o
	obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-8996.o		obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-8996.o

drivers/clk/qcom/mdss/mdss-dsi-pll.h

+7 −1

Original line number	Original line	Diff line number	Diff line
	@@ -50,6 +50,13 @@ static inline struct dsi_pll_vco_clk to_vco_clk(struct clk clk)
	return container_of(clk, struct dsi_pll_vco_clk, c);		return container_of(clk, struct dsi_pll_vco_clk, c);
	}		}

			static inline int dsi_pll_div_prepare(struct clk *c)
			{
			struct div_clk *div = to_div_clk(c);
			/* Restore the divider's value */
			return div->ops->set_div(div, div->data.div);
			}

	int dsi_pll_clock_register_hpm(struct platform_device *pdev,		int dsi_pll_clock_register_hpm(struct platform_device *pdev,
	struct mdss_pll_resources *pll_res);		struct mdss_pll_resources *pll_res);
	int dsi_pll_clock_register_20nm(struct platform_device *pdev,		int dsi_pll_clock_register_20nm(struct platform_device *pdev,
	@@ -61,7 +68,6 @@ int dsi_pll_clock_register_8996(struct platform_device *pdev,

	int set_byte_mux_sel(struct mux_clk *clk, int sel);		int set_byte_mux_sel(struct mux_clk *clk, int sel);
	int get_byte_mux_sel(struct mux_clk *clk);		int get_byte_mux_sel(struct mux_clk *clk);
	int dsi_pll_div_prepare(struct clk *c);
	int dsi_pll_mux_prepare(struct clk *c);		int dsi_pll_mux_prepare(struct clk *c);
	int fixed_4div_set_div(struct div_clk *clk, int div);		int fixed_4div_set_div(struct div_clk *clk, int div);
	int fixed_4div_get_div(struct div_clk *clk);		int fixed_4div_get_div(struct div_clk *clk);

drivers/clk/qcom/mdss/mdss-edp-pll.h

deleted100644 → 0

+0 −27

Original line number	Original line	Diff line number	Diff line
	/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License version 2 and
	* only version 2 as published by the Free Software Foundation.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*/

	#ifndef __MDSS_EDP_PLL_H
	#define __MDSS_EDP_PLL_H

	struct edp_pll_vco_clk {
	unsigned long ref_clk_rate;
	unsigned long rate; /* vco rate */
	unsigned long *rate_list;
	void *priv;

	struct clk c;
	};

	int edp_pll_clock_register(struct platform_device *pdev,
	struct mdss_pll_resources *pll_res);
	#endif

drivers/clk/qcom/mdss/mdss-pll.c

+3 −84

Original line number	Original line	Diff line number	Diff line
	@@ -22,7 +22,6 @@
	#include <linux/clk/msm-clock-generic.h>		#include <linux/clk/msm-clock-generic.h>

	#include "mdss-pll.h"		#include "mdss-pll.h"
	#include "mdss-edp-pll.h"
	#include "mdss-dsi-pll.h"		#include "mdss-dsi-pll.h"
	#include "mdss-hdmi-pll.h"		#include "mdss-hdmi-pll.h"

	@@ -128,35 +127,9 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
	goto err;		goto err;
	}		}

	if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8916")) {		if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8996")) {
	pll_res->pll_interface_type = MDSS_DSI_PLL_LPM;
	pll_res->target_id = MDSS_PLL_TARGET_8916;
	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8939")) {
	pll_res->pll_interface_type = MDSS_DSI_PLL_LPM;
	pll_res->target_id = MDSS_PLL_TARGET_8939;
	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8909")) {
	pll_res->pll_interface_type = MDSS_DSI_PLL_LPM;
	pll_res->target_id = MDSS_PLL_TARGET_8909;
	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8974")) {
	pll_res->pll_interface_type = MDSS_DSI_PLL_HPM;
	pll_res->target_id = MDSS_PLL_TARGET_8974;
	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8994")) {
	pll_res->pll_interface_type = MDSS_DSI_PLL_20NM;
	pll_res->target_id = MDSS_PLL_TARGET_8994;
	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8992")) {
	pll_res->pll_interface_type = MDSS_DSI_PLL_20NM;
	pll_res->target_id = MDSS_PLL_TARGET_8992;
	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8996")) {
	pll_res->pll_interface_type = MDSS_DSI_PLL_8996;		pll_res->pll_interface_type = MDSS_DSI_PLL_8996;
	pll_res->target_id = MDSS_PLL_TARGET_8996;		pll_res->target_id = MDSS_PLL_TARGET_8996;
	} else if (!strcmp(compatible_stream, "qcom,mdss_edp_pll")) {
	pll_res->pll_interface_type = MDSS_EDP_PLL;
	} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll")) {
	pll_res->pll_interface_type = MDSS_HDMI_PLL;
	} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8994")) {
	pll_res->pll_interface_type = MDSS_HDMI_PLL_20NM;
	} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8992")) {
	pll_res->pll_interface_type = MDSS_HDMI_PLL_20NM;
	} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996")) {		} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996")) {
	pll_res->pll_interface_type = MDSS_HDMI_PLL_8996;		pll_res->pll_interface_type = MDSS_HDMI_PLL_8996;
	} else {		} else {
	@@ -182,27 +155,10 @@ static int mdss_pll_clock_register(struct platform_device *pdev,
	}		}

	switch (pll_res->pll_interface_type) {		switch (pll_res->pll_interface_type) {
	case MDSS_DSI_PLL_LPM:
	rc = dsi_pll_clock_register_lpm(pdev, pll_res);
	break;
	case MDSS_DSI_PLL_HPM:
	rc = dsi_pll_clock_register_hpm(pdev, pll_res);
	break;
	case MDSS_DSI_PLL_20NM:
	rc = dsi_pll_clock_register_20nm(pdev, pll_res);
	break;
	case MDSS_DSI_PLL_8996:		case MDSS_DSI_PLL_8996:
	rc = dsi_pll_clock_register_8996(pdev, pll_res);		rc = dsi_pll_clock_register_8996(pdev, pll_res);
	break;		break;
	case MDSS_EDP_PLL:		case MDSS_HDMI_PLL_8996:
	rc = edp_pll_clock_register(pdev, pll_res);
	break;
	case MDSS_HDMI_PLL:
	rc = hdmi_pll_clock_register(pdev, pll_res);
	case MDSS_HDMI_PLL_20NM:
	rc = hdmi_20nm_pll_clock_register(pdev, pll_res);
	break;
	case MDSS_HDMI_PLL_THULIUM:
	rc = hdmi_8996_pll_clock_register(pdev, pll_res);		rc = hdmi_8996_pll_clock_register(pdev, pll_res);
	break;		break;
	case MDSS_UNKNOWN_PLL:		case MDSS_UNKNOWN_PLL:
	@@ -279,36 +235,9 @@ static int mdss_pll_probe(struct platform_device *pdev)
	goto res_parse_error;		goto res_parse_error;
	}		}

	/*
	* DSI PLL 1 is leaking current whenever MDSS GDSC is toggled. Need to
	* map PLL1 registers along with the PLl0 so that we can manually turn
	* off PLL1.
	*/
	if (pll_res->pll_interface_type == MDSS_DSI_PLL_20NM) {
	struct resource *pll_1_base_reg;

	pll_1_base_reg = platform_get_resource_byname(pdev,
	IORESOURCE_MEM, "pll_1_base");
	if (pll_1_base_reg) {
	pll_res->pll_1_base = ioremap(pll_1_base_reg->start,
	resource_size(pll_1_base_reg));
	if (!pll_res->pll_1_base)
	pr_err("Unable to remap pll 1 base resources\n");
	} else {
	pr_err("Unable to get the pll 1 base resource\n");
	}
	}

	phy_base_reg = platform_get_resource_byname(pdev,		phy_base_reg = platform_get_resource_byname(pdev,
	IORESOURCE_MEM, "phy_base");		IORESOURCE_MEM, "phy_base");
	if (!phy_base_reg) {		if (phy_base_reg) {
	/* This resource is mandatory for HDMI pll */
	if (pll_res->pll_interface_type == MDSS_HDMI_PLL) {
	pr_err("Unable to get the phy base resources\n");
	rc = -ENOMEM;
	goto phy_io_error;
	}
	} else {
	pll_res->phy_base = ioremap(phy_base_reg->start,		pll_res->phy_base = ioremap(phy_base_reg->start,
	resource_size(phy_base_reg));		resource_size(phy_base_reg));
	if (!pll_res->phy_base) {		if (!pll_res->phy_base) {
	@@ -404,18 +333,8 @@ static int mdss_pll_remove(struct platform_device *pdev)
	}		}

	static const struct of_device_id mdss_pll_dt_match[] = {		static const struct of_device_id mdss_pll_dt_match[] = {
	{.compatible = "qcom,mdss_dsi_pll_8974"},
	{.compatible = "qcom,mdss_dsi_pll_8994"},
	{.compatible = "qcom,mdss_dsi_pll_8996"},		{.compatible = "qcom,mdss_dsi_pll_8996"},
	{.compatible = "qcom,mdss_hdmi_pll_8994"},
	{.compatible = "qcom,mdss_dsi_pll_8992"},
	{.compatible = "qcom,mdss_hdmi_pll_8992"},
	{.compatible = "qcom,mdss_hdmi_pll_8996"},		{.compatible = "qcom,mdss_hdmi_pll_8996"},
	{.compatible = "qcom,mdss_dsi_pll_8916"},
	{.compatible = "qcom,mdss_dsi_pll_8939"},
	{.compatible = "qcom,mdss_dsi_pll_8909"},
	{.compatible = "qcom,mdss_edp_pll"},
	{.compatible = "qcom,mdss_hdmi_pll"},
	{}		{}
	};		};

drivers/clk/qcom/mdss/mdss-pll.h

+1 −13

Original line number	Original line	Diff line number	Diff line
	@@ -28,25 +28,13 @@
	(base) + (offset))		(base) + (offset))

	enum {		enum {
	MDSS_DSI_PLL_LPM,
	MDSS_DSI_PLL_HPM,
	MDSS_DSI_PLL_20NM,
	MDSS_DSI_PLL_8996,		MDSS_DSI_PLL_8996,
	MDSS_EDP_PLL,		MDSS_HDMI_PLL_8996,
	MDSS_HDMI_PLL,
	MDSS_HDMI_PLL_20NM,
	MDSS_HDMI_PLL_THULIUM,
	MDSS_UNKNOWN_PLL,		MDSS_UNKNOWN_PLL,
	};		};

	enum {		enum {
	MDSS_PLL_TARGET_8974,
	MDSS_PLL_TARGET_8994,
	MDSS_PLL_TARGET_8992,
	MDSS_PLL_TARGET_8996,		MDSS_PLL_TARGET_8996,
	MDSS_PLL_TARGET_8916,
	MDSS_PLL_TARGET_8939,
	MDSS_PLL_TARGET_8909,
	};		};

	struct mdss_pll_resources {		struct mdss_pll_resources {