Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 77cadd10 authored by Clarence Ip's avatar Clarence Ip
Browse files

msm: sde: check stride alignment before disabling partial writes 



Only disable partial writes if the stride is a multiple of 32
bytes. Otherwise, the partial read-modify-write behavior is
needed to avoid corrupting the output image.

CRs-Fixed: 2056485
Change-Id: Ia86dfc4561f96f7774db1e8529ee5a553c584426
Signed-off-by: default avatarClarence Ip <cip@codeaurora.org>
parent 3b1e2c6a

drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c

+32 −5
Original line number Diff line number Diff line
@@ -57,6 +57,9 @@ 


#define DEFAULT_MAXLINEWIDTH	4096



/* stride alignment requirement for avoiding partial writes */

#define PARTIAL_WRITE_ALIGNMENT	0x1F



/* Macro for constructing the REGDMA command */

#define SDE_REGDMA_WRITE(p, off, data) \

	do { \
@@ -869,6 +872,8 @@ static void sde_hw_rotator_setup_timestamp_packet( 
	SDE_REGDMA_WRITE(wrptr, ROT_WB_OUT_SIZE, 0x00010001);

	SDE_REGDMA_WRITE(wrptr, ROT_WB_OUT_IMG_SIZE, 0x00010001);

	SDE_REGDMA_WRITE(wrptr, ROT_WB_OUT_XY, 0);

	SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_WRITE_CONFIG,

			(ctx->rot->highest_bank & 0x3) << 8);

	SDE_REGDMA_WRITE(wrptr, ROTTOP_DNSC, 0);

	SDE_REGDMA_WRITE(wrptr, ROTTOP_OP_MODE, 1);

	SDE_REGDMA_MODIFY(wrptr, REGDMA_TIMESTAMP_REG, mask, swts);
@@ -1270,7 +1275,7 @@ static void sde_hw_rotator_setup_wbengine(struct sde_hw_rotator_context *ctx, 
	u32 *wrptr;

	u32 pack = 0;

	u32 dst_format = 0;

	u32 partial_write = 0;

	u32 no_partial_writes = 0;

	int i;



	wrptr = sde_hw_rotator_get_regdma_segment(ctx);
@@ -1355,12 +1360,34 @@ static void sde_hw_rotator_setup_wbengine(struct sde_hw_rotator_context *ctx, 
			(cfg->h_downscale_factor << 16));



	/* partial write check */

	if (test_bit(SDE_CAPS_PARTIALWR, mdata->sde_caps_map) &&

			!sde_mdp_is_ubwc_format(fmt))

		partial_write = BIT(10);

	if (test_bit(SDE_CAPS_PARTIALWR, mdata->sde_caps_map)) {

		no_partial_writes = BIT(10);



		/*

		 * For simplicity, don't disable partial writes if

		 * the ROI does not span the entire width of the

		 * output image, and require the total stride to

		 * also be properly aligned.

		 *

		 * This avoids having to determine the memory access

		 * alignment of the actual horizontal ROI on a per

		 * color format basis.

		 */

		if (sde_mdp_is_ubwc_format(fmt)) {

			no_partial_writes = 0x0;

		} else if (cfg->dst_rect->x ||

				cfg->dst_rect->w != cfg->img_width) {

			no_partial_writes = 0x0;

		} else {

			for (i = 0; i < SDE_ROT_MAX_PLANES; i++)

				if (cfg->dst_plane.ystride[i] &

						PARTIAL_WRITE_ALIGNMENT)

					no_partial_writes = 0x0;

		}

	}



	/* write config setup for bank configuration */

	SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_WRITE_CONFIG, partial_write |

	SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_WRITE_CONFIG, no_partial_writes |

			(ctx->rot->highest_bank & 0x3) << 8);



	if (test_bit(SDE_CAPS_UBWC_2, mdata->sde_caps_map))