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Commit 760bb977 authored Aug 01, 2015 by Heiko Stuebner

ARM: dts: rockchip: add usb phys to Cortex-A9 socs

This adds the usbphy nodes to rk3066 and rk3188, which share the usb hosts
in rk3xxx.dtsi and also enables it on boards based around these socs.

The usb-phy itself is the same as used on the rk3288 already.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>

parent ec32bd9f

arch/arm/boot/dts/rk3066a-marsboard.dts

+4 −0

Original line number	Diff line number	Diff line
		@@ -202,6 +202,10 @@
		status = "okay";
		};

		&usbphy {
		status = "okay";
		};

		&wdt {
		status = "okay";
		};

arch/arm/boot/dts/rk3066a-rayeager.dts

+4 −0

Original line number	Diff line number	Diff line
		@@ -460,6 +460,10 @@
		status = "okay";
		};

		&usbphy {
		status = "okay";
		};

		&usb_otg {
		status = "okay";
		};

arch/arm/boot/dts/rk3066a.dtsi

+22 −0

Original line number	Diff line number	Diff line
		@@ -169,6 +169,28 @@
		clock-names = "timer", "pclk";
		};

		usbphy: phy {
		compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		usbphy0: usb-phy0 {
		#phy-cells = <0>;
		reg = <0x17c>;
		clocks = <&cru SCLK_OTGPHY0>;
		clock-names = "phyclk";
		};

		usbphy1: usb-phy1 {
		#phy-cells = <0>;
		reg = <0x188>;
		clocks = <&cru SCLK_OTGPHY1>;
		clock-names = "phyclk";
		};
		};

		pinctrl: pinctrl {
		compatible = "rockchip,rk3066a-pinctrl";
		rockchip,grf = <&grf>;

arch/arm/boot/dts/rk3188-radxarock.dts

+4 −0

Original line number	Diff line number	Diff line
		@@ -359,6 +359,10 @@
		status = "okay";
		};

		&usbphy {
		status = "okay";
		};

		&usb_host {
		status = "okay";
		};

arch/arm/boot/dts/rk3188.dtsi

+22 −0

Original line number	Diff line number	Diff line
		@@ -130,6 +130,28 @@
		#reset-cells = <1>;
		};

		usbphy: phy {
		compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		usbphy0: usb-phy0 {
		#phy-cells = <0>;
		reg = <0x10c>;
		clocks = <&cru SCLK_OTGPHY0>;
		clock-names = "phyclk";
		};

		usbphy1: usb-phy1 {
		#phy-cells = <0>;
		reg = <0x11c>;
		clocks = <&cru SCLK_OTGPHY1>;
		clock-names = "phyclk";
		};
		};

		pinctrl: pinctrl {
		compatible = "rockchip,rk3188-pinctrl";
		rockchip,grf = <&grf>;