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Commit 7405f42c authored by Tom O'Rourke's avatar Tom O'Rourke Committed by Daniel Vetter
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drm/i915/chv: Fix "drm/i915/chv: Add a bunch of pre production workarounds" 



Correct a merge mishap in commit e4443e45.

Wa*:chv belongs in cherryview_enable_rps, not gen8_enable_rps.

Signed-off-by: default avatarTom O'Rourke <Tom.O'Rourke@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3b2cc8ab

drivers/gpu/drm/i915/intel_pm.c

+6 −6
Original line number Diff line number Diff line
@@ -3513,15 +3513,11 @@ static void gen8_enable_rps(struct drm_device *dev) 


	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);



	/* WaDisablePwrmtrEvent:chv (pre-production hw) */

	I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);

	I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);



	/* 5: Enable RPS */

	I915_WRITE(GEN6_RP_CONTROL,

		   GEN6_RP_MEDIA_TURBO |

		   GEN6_RP_MEDIA_HW_NORMAL_MODE |

		   GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */

		   GEN6_RP_MEDIA_IS_GFX |

		   GEN6_RP_ENABLE |

		   GEN6_RP_UP_BUSY_AVG |

		   GEN6_RP_DOWN_IDLE_AVG);
@@ -4015,10 +4011,14 @@ static void cherryview_enable_rps(struct drm_device *dev) 


	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);



	/* WaDisablePwrmtrEvent:chv (pre-production hw) */

	I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);

	I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);



	/* 5: Enable RPS */

	I915_WRITE(GEN6_RP_CONTROL,

		   GEN6_RP_MEDIA_HW_NORMAL_MODE |

		   GEN6_RP_MEDIA_IS_GFX |

		   GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */

		   GEN6_RP_ENABLE |

		   GEN6_RP_UP_BUSY_AVG |

		   GEN6_RP_DOWN_IDLE_AVG);