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Commit 6fa7aec1 authored by Vandana Kannan's avatar Vandana Kannan Committed by Daniel Vetter
Browse files

drm/i915: Support for RR switching on VLV 



Definition of VLV RR switch bit and corresponding toggling in
set_drrs function.

Signed-off-by: default avatarVandana Kannan <vandana.kannan@intel.com>
Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a4c30b1d

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -3916,6 +3916,7 @@ enum skl_disp_power_wells { 
#define   PIPECONF_INTERLACE_MODE_MASK		(7 << 21)

#define   PIPECONF_EDP_RR_MODE_SWITCH		(1 << 20)

#define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)

#define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)

#define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)

#define   PIPECONF_BPC_MASK	(0x7 << 5)

#define   PIPECONF_8BPC		(0<<5)

drivers/gpu/drm/i915/intel_dp.c

+8 −2
Original line number Diff line number Diff line
@@ -4825,8 +4825,14 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) 
		val = I915_READ(reg);



		if (index > DRRS_HIGH_RR) {

			if (IS_VALLEYVIEW(dev))

				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;

			else

				val |= PIPECONF_EDP_RR_MODE_SWITCH;

		} else {

			if (IS_VALLEYVIEW(dev))

				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;

			else

				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;

		}

		I915_WRITE(reg, val);