Commit a4c30b1d authored Feb 13, 2015 by Vandana Kannan Committed by Daniel Vetter Feb 24, 2015

drm/i915/bdw: Add support for DRRS to switch RR



For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M & N registers and the new M/N values will be used in the next frame
that is output.

V2: [By Ram]: intel_dp_set_m_n() is rewritten to accommodate
	gen >= 8 [Rodrigo]
V3: Coding style correction [Ram]
V4: [By Ram] intel_dp_set_m_n modifications are moved into a
	separate patch, retaining only DRRS related changes here [Rodrigo]

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent fe3cd48d

drivers/gpu/drm/i915/intel_dp.c

+14 −2

Original line number	Diff line number	Diff line
		@@ -4808,12 +4808,24 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
		return;
		}

		if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
		if (INTEL_INFO(dev)->gen >= 8) {
		switch (index) {
		case DRRS_HIGH_RR:
		intel_dp_set_m_n(intel_crtc, M1_N1);
		break;
		case DRRS_LOW_RR:
		intel_dp_set_m_n(intel_crtc, M2_N2);
		break;
		case DRRS_MAX_RR:
		default:
		DRM_ERROR("Unsupported refreshrate type\n");
		}
		} else if (INTEL_INFO(dev)->gen > 6) {
		reg = PIPECONF(intel_crtc->config->cpu_transcoder);
		val = I915_READ(reg);

		if (index > DRRS_HIGH_RR) {
		val \|= PIPECONF_EDP_RR_MODE_SWITCH;
		intel_dp_set_m_n(intel_crtc);
		} else {
		val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
		}