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Commit 6f354e5f authored by Russell King's avatar Russell King
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ARM: pm: CPU specific code should not overwrite r1 (v:p offset) 



r1 stores the v:p offset from the CPU invariant resume code, and is
expected to be preserved by the CPU specific code.  Overwriting it is
not a good idea.

We've managed to get away with it on sa1100 platforms because most
happen to have PHYS_OFFSET == PAGE_OFFSET, but that may not be the
case depending on kernel configuration.  So fix this latent bug.

This fixes xsc3 as well which was saving and restoring this register
independently.

Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 0f81bb6b

arch/arm/mm/proc-sa1100.S

+5 −5
Original line number Diff line number Diff line
@@ -182,11 +182,11 @@ ENDPROC(cpu_sa1100_do_suspend) 


ENTRY(cpu_sa1100_do_resume)

	ldmia	r0, {r4 - r7}			@ load cp regs

	mov	r1, #0

	mcr	p15, 0, r1, c8, c7, 0		@ flush I+D TLBs

	mcr	p15, 0, r1, c7, c7, 0		@ flush I&D cache

	mcr	p15, 0, r1, c9, c0, 0		@ invalidate RB

	mcr	p15, 0, r1, c9, c0, 5		@ allow user space to use RB

	mov	ip, #0

	mcr	p15, 0, ip, c8, c7, 0		@ flush I+D TLBs

	mcr	p15, 0, ip, c7, c7, 0		@ flush I&D cache

	mcr	p15, 0, ip, c9, c0, 0		@ invalidate RB

	mcr	p15, 0, ip, c9, c0, 5		@ allow user space to use RB



	mcr	p15, 0, r4, c3, c0, 0		@ domain ID

	mcr	p15, 0, r5, c2, c0, 0		@ translation table base addr

arch/arm/mm/proc-xsc3.S

+3 −3
Original line number Diff line number Diff line
@@ -406,7 +406,7 @@ ENTRY(cpu_xsc3_set_pte_ext) 
	.align



.globl	cpu_xsc3_suspend_size

.equ	cpu_xsc3_suspend_size, 4 * 8

.equ	cpu_xsc3_suspend_size, 4 * 7

#ifdef CONFIG_PM_SLEEP

ENTRY(cpu_xsc3_do_suspend)

	stmfd	sp!, {r4 - r10, lr}
@@ -418,12 +418,12 @@ ENTRY(cpu_xsc3_do_suspend) 
	mrc	p15, 0, r9, c1, c0, 1	@ auxiliary control reg

	mrc 	p15, 0, r10, c1, c0, 0	@ control reg

	bic	r4, r4, #2		@ clear frequency change bit

	stmia	r0, {r1, r4 - r10}	@ store v:p offset + cp regs

	stmia	r0, {r4 - r10}		@ store cp regs

	ldmia	sp!, {r4 - r10, pc}

ENDPROC(cpu_xsc3_do_suspend)



ENTRY(cpu_xsc3_do_resume)

	ldmia	r0, {r1, r4 - r10}	@ load v:p offset + cp regs

	ldmia	r0, {r4 - r10}		@ load cp regs

	mov	ip, #0

	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I & D caches, BTB

	mcr	p15, 0, ip, c7, c10, 4	@ drain write (&fill) buffer