Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6c6c185b authored by Sachin Kamat's avatar Sachin Kamat Committed by Kukjin Kim
Browse files

ARM: EXYNOS: Add G2D related clock entries for SMDK4X12 



Adds G2D related clock entries for SMDK4X12 boards.

Signed-off-by: default avatarSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 8bf56466

arch/arm/mach-exynos/clock-exynos4212.c

+39 −2
Original line number Diff line number Diff line
@@ -68,12 +68,45 @@ static struct clksrc_clk clk_mout_mpll_user = { 
	.reg_src	= { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },

};



static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {

	.clk	= {

		.name		= "mout_g2d0",

	},

	.sources = &exynos4_clkset_mout_g2d0,

	.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },

};



static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {

	.clk	= {

		.name		= "mout_g2d1",

	},

	.sources = &exynos4_clkset_mout_g2d1,

	.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },

};



static struct clk *exynos4x12_clkset_mout_g2d_list[] = {

	[0] = &exynos4x12_clk_mout_g2d0.clk,

	[1] = &exynos4x12_clk_mout_g2d1.clk,

};



static struct clksrc_sources exynos4x12_clkset_mout_g2d = {

	.sources	= exynos4x12_clkset_mout_g2d_list,

	.nr_sources	= ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),

};



static struct clksrc_clk *sysclks[] = {

	&clk_mout_mpll_user,

};



static struct clksrc_clk clksrcs[] = {

	/* nothing here yet */

	{

		.clk	= {

			.name		= "sclk_fimg2d",

		},

		.sources = &exynos4x12_clkset_mout_g2d,

		.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },

		.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },

	},

};



static struct clk init_clocks_off[] = {
@@ -102,7 +135,11 @@ static struct clk init_clocks_off[] = { 
		.devname	= "exynos-fimc-lite.1",

		.enable		= exynos4212_clk_ip_isp0_ctrl,

		.ctrlbit	= (1 << 3),

	}

	}, {

		.name		= "fimg2d",

		.enable		= exynos4_clk_ip_dmc_ctrl,

		.ctrlbit	= (1 << 23),

	},

};



#ifdef CONFIG_PM_SLEEP