Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8bf56466 authored by Sachin Kamat's avatar Sachin Kamat Committed by Kukjin Kim
Browse files

ARM: EXYNOS: Move G2D clock entries to clock-exynos4210.c file 



G2D clock registers are different in EXYNOS4210 and EXYNOS4X12 SoCs.
Hence moving the SoC specific G2D clock entries from common clock file
(clock-exynos4.c) to EXYNOS4210 specific clock file (clock-exynos4210.c).

Signed-off-by: default avatarSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 84a1caf1

arch/arm/mach-exynos/clock-exynos4.c

+2 −39
Original line number Diff line number Diff line
@@ -619,10 +619,6 @@ static struct clk exynos4_init_clocks_off[] = { 
		.devname	= "samsung-ac97",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 27),

	}, {

		.name		= "fimg2d",

		.enable		= exynos4_clk_ip_image_ctrl,

		.ctrlbit	= (1 << 0),

	}, {

		.name		= "mfc",

		.devname	= "s5p-mfc",
@@ -819,47 +815,21 @@ static struct clk *exynos4_clkset_mout_g2d0_list[] = { 
	[1] = &exynos4_clk_sclk_apll.clk,

};



static struct clksrc_sources exynos4_clkset_mout_g2d0 = {

struct clksrc_sources exynos4_clkset_mout_g2d0 = {

	.sources	= exynos4_clkset_mout_g2d0_list,

	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),

};



static struct clksrc_clk exynos4_clk_mout_g2d0 = {

	.clk	= {

		.name		= "mout_g2d0",

	},

	.sources = &exynos4_clkset_mout_g2d0,

	.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },

};



static struct clk *exynos4_clkset_mout_g2d1_list[] = {

	[0] = &exynos4_clk_mout_epll.clk,

	[1] = &exynos4_clk_sclk_vpll.clk,

};



static struct clksrc_sources exynos4_clkset_mout_g2d1 = {

struct clksrc_sources exynos4_clkset_mout_g2d1 = {

	.sources	= exynos4_clkset_mout_g2d1_list,

	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),

};



static struct clksrc_clk exynos4_clk_mout_g2d1 = {

	.clk	= {

		.name		= "mout_g2d1",

	},

	.sources = &exynos4_clkset_mout_g2d1,

	.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },

};



static struct clk *exynos4_clkset_mout_g2d_list[] = {

	[0] = &exynos4_clk_mout_g2d0.clk,

	[1] = &exynos4_clk_mout_g2d1.clk,

};



static struct clksrc_sources exynos4_clkset_mout_g2d = {

	.sources	= exynos4_clkset_mout_g2d_list,

	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d_list),

};



static struct clk *exynos4_clkset_mout_mfc0_list[] = {

	[0] = &exynos4_clk_mout_mpll.clk,

	[1] = &exynos4_clk_sclk_apll.clk,
@@ -1124,13 +1094,6 @@ static struct clksrc_clk exynos4_clksrcs[] = { 
		.sources = &exynos4_clkset_group,

		.reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },

		.reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },

	}, {

		.clk	= {

			.name		= "sclk_fimg2d",

		},

		.sources = &exynos4_clkset_mout_g2d,

		.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },

		.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },

	}, {

		.clk	= {

			.name		= "sclk_mfc",

arch/arm/mach-exynos/clock-exynos4.h

+3 −0
Original line number Diff line number Diff line
@@ -23,6 +23,9 @@ extern struct clksrc_sources exynos4_clkset_group; 
extern struct clk *exynos4_clkset_aclk_top_list[];

extern struct clk *exynos4_clkset_group_list[];



extern struct clksrc_sources exynos4_clkset_mout_g2d0;

extern struct clksrc_sources exynos4_clkset_mout_g2d1;



extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);

extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);

extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);

arch/arm/mach-exynos/clock-exynos4210.c

+37 −0
Original line number Diff line number Diff line
@@ -48,6 +48,32 @@ static struct clksrc_clk *sysclks[] = { 
	/* nothing here yet */

};



static struct clksrc_clk exynos4210_clk_mout_g2d0 = {

	.clk	= {

		.name		= "mout_g2d0",

	},

	.sources = &exynos4_clkset_mout_g2d0,

	.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },

};



static struct clksrc_clk exynos4210_clk_mout_g2d1 = {

	.clk	= {

		.name		= "mout_g2d1",

	},

	.sources = &exynos4_clkset_mout_g2d1,

	.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },

};



static struct clk *exynos4210_clkset_mout_g2d_list[] = {

	[0] = &exynos4210_clk_mout_g2d0.clk,

	[1] = &exynos4210_clk_mout_g2d1.clk,

};



static struct clksrc_sources exynos4210_clkset_mout_g2d = {

	.sources	= exynos4210_clkset_mout_g2d_list,

	.nr_sources	= ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),

};



static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)

{

	return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
@@ -74,6 +100,13 @@ static struct clksrc_clk clksrcs[] = { 
		.sources = &exynos4_clkset_group,

		.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },

		.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },

	}, {

		.clk	= {

			.name		= "sclk_fimg2d",

		},

		.sources = &exynos4210_clkset_mout_g2d,

		.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },

		.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },

	},

};
@@ -105,6 +138,10 @@ static struct clk init_clocks_off[] = { 
		.devname	= SYSMMU_CLOCK_DEVNAME(fimd1, 11),

		.enable		= exynos4_clk_ip_lcd1_ctrl,

		.ctrlbit	= (1 << 4),

	}, {

		.name		= "fimg2d",

		.enable		= exynos4_clk_ip_image_ctrl,

		.ctrlbit	= (1 << 0),

	},

};