Commit 6b698516 authored Nov 28, 2015 by Daniel Vetter

drm/i915: fix fdi related fifo underruns on hsw

Similar to

commit 37ca8d4c
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date:   Fri Oct 30 19:20:27 2015 +0200

    drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB

we can only enable fifo underrun reporting when using the fdi/lpt
after everything is set up and after a bit of waiting. The waiting
is required, enabling it right after enabling encoders will first trigger
an underrun on the pch and then, 1 frame later, an underrun on the
cpu. Two vblank waits after encoder enabling seems enough to curb it.

And similar to

Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date:   Fri Nov 20 22:09:18 2015 +0200

    drm/i915: Suppress spurious CPU FIFO underruns on ILK-IVB

we also need to make sure cpu fifo underrun reporting is disabled when
enabling the fdi rx/tx and pch transcoder&port. But somehow this is
only needed when enabling, not also when disabling.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1448705139-12534-1-git-send-email-daniel.vetter@ffwll.ch
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91578


Tested-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent a65347ba

drivers/gpu/drm/i915/intel_display.c

+10 −2

Original line number	Diff line number	Diff line
		@@ -4978,7 +4978,11 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)

		intel_crtc->active = true;

		if (intel_crtc->config->has_pch_encoder)
		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
		else
		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);

		for_each_encoder_on_crtc(dev, crtc, encoder) {
		if (encoder->pre_enable)
		encoder->pre_enable(encoder);
		@@ -5022,9 +5026,13 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
		intel_opregion_notify_encoder(encoder, true);
		}

		if (intel_crtc->config->has_pch_encoder)
		if (intel_crtc->config->has_pch_encoder) {
		intel_wait_for_vblank(dev, pipe);
		intel_wait_for_vblank(dev, pipe);
		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
		true);
		}

		/* If we change the relative order between pipe/planes enabling, we need
		* to change the workaround. */