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Commit 62ba1928 authored by Patrick Daly's avatar Patrick Daly
Browse files

iommu: arm-smmu: Standardize atos disablement feature 



Make this a devicetree property instead of tying it to a specific
iommu model. Future revisions of this iommu model may not have the
same issue.

Change-Id: I2274644db05b1967c8f368d99b74cd00fdeb1af2
Signed-off-by: default avatarPatrick Daly <pdaly@codeaurora.org>
parent 48c0b07e

Documentation/devicetree/bindings/iommu/arm,smmu.txt

+4 −0
Original line number Diff line number Diff line
@@ -96,6 +96,10 @@ conditions. 
		  retention. No cache invalidation operations involving asid

		  may be used.



- qcom,disable-atos:

		  Some hardware may not have full support for atos debugging

		  in tandem with other features like power collapse.



- qcom,deferred-regulator-disable-delay : The time delay for deferred regulator

                  disable in ms. In case of unmap call, regulator is

                  enabled/disabled. This may introduce additional delay. For

arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm845.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
		#iommu-cells = <1>;

		qcom,dynamic;

		qcom,use-3-lvl-tables;

		qcom,disable-atos;

		#global-interrupts = <2>;

		qcom,regulator-names = "vdd";

		vdd-supply = <&gpu_cx_gdsc>;
@@ -62,6 +63,7 @@ 
		qcom,skip-init;

		qcom,use-3-lvl-tables;

		qcom,no-asid-retention;

		qcom,disable-atos;

		#global-interrupts = <1>;

		#size-cells = <1>;

		#address-cells = <1>;

drivers/iommu/arm-smmu.c

+6 −5
Original line number Diff line number Diff line
@@ -427,6 +427,7 @@ struct arm_smmu_device { 
#define ARM_SMMU_OPT_DYNAMIC		(1 << 3)

#define ARM_SMMU_OPT_3LVL_TABLES	(1 << 4)

#define ARM_SMMU_OPT_NO_ASID_RETENTION	(1 << 5)

#define ARM_SMMU_OPT_DISABLE_ATOS	(1 << 6)

	u32				options;

	enum arm_smmu_arch_version	version;

	enum arm_smmu_implementation	model;
@@ -547,6 +548,7 @@ static struct arm_smmu_option_prop arm_smmu_options[] = { 
	{ ARM_SMMU_OPT_DYNAMIC, "qcom,dynamic" },

	{ ARM_SMMU_OPT_3LVL_TABLES, "qcom,use-3-lvl-tables" },

	{ ARM_SMMU_OPT_NO_ASID_RETENTION, "qcom,no-asid-retention" },

	{ ARM_SMMU_OPT_DISABLE_ATOS, "qcom,disable-atos" },

	{ 0, NULL},

};
@@ -2490,6 +2492,10 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain, 
	phys_addr_t ret = 0;

	unsigned long flags;

	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);

	struct arm_smmu_device *smmu = smmu_domain->smmu;



	if (smmu->options & ARM_SMMU_OPT_DISABLE_ATOS)

		return 0;



	if (smmu_domain->smmu->arch_ops &&

	    smmu_domain->smmu->arch_ops->iova_to_phys_hard) {
@@ -3265,11 +3271,6 @@ static phys_addr_t qsmmuv2_iova_to_phys_hard(struct iommu_domain *domain, 
	u32 sctlr, sctlr_orig, fsr;

	void __iomem *cb_base;



	if (smmu->model == QCOM_SMMUV2) {

		dev_err(smmu->dev, "ATOS support is disabled\n");

		return 0;

	}



	ret = arm_smmu_power_on(smmu_domain->smmu->pwr);

	if (ret)

		return ret;