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Commit 48c0b07e authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "soc: qcom: pil: Take MSS PDC offset from DT"

parents 0172d8a0 506c07fc

Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt

+3 −0
Original line number Diff line number Diff line
@@ -67,6 +67,9 @@ Optional properties: 
			  service.

- qcom,sysmon-id:	platform device id that sysmon is probed with for the subsystem.

- qcom,override-acc: Boolean- Present if we need to override the default ACC settings

- qcom,mss_pdc_offset: Integer- Mandatory if PDC register is specified. It is

				used to specify which bit in the PDC register

				corresponds to the modem.

- qcom,ahb-clk-vote: Boolean- Present if we need to remove the vote for the mss_cfg_ahb

		     clock after the modem boots up

- qcom,pnoc-clk-vote: Boolean- Present if the modem needs the PNOC bus to be

arch/arm64/boot/dts/qcom/sdm670.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -1690,6 +1690,7 @@ 
		qcom,ssctl-instance-id = <0x12>;

		qcom,override-acc;

		qcom,qdsp6v65-1-0;

		qcom,mss_pdc_offset = <8>;

		status = "ok";

		memory-region = <&pil_modem_mem>;

		qcom,mem-protect-id = <0xF>;

arch/arm64/boot/dts/qcom/sdm845-v2.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -477,6 +477,10 @@ 
	};

};



&pil_modem {

	qcom,mss_pdc_offset = <9>;

};



/* VDD_APC0 */

&pm8998_s13 {

	regulator-min-microvolt = <568000>;

arch/arm64/boot/dts/qcom/sdm845.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -1742,6 +1742,7 @@ 
		qcom,ssctl-instance-id = <0x12>;

		qcom,override-acc;

		qcom,qdsp6v65-1-0;

		qcom,mss_pdc_offset = <8>;

		status = "ok";

		memory-region = <&pil_modem_mem>;

		qcom,mem-protect-id = <0xF>;

drivers/soc/qcom/pil-msa.c

+3 −5
Original line number Diff line number Diff line
@@ -77,9 +77,6 @@ 


#define MSS_MAGIC			0XAABADEAD



#define MSS_PDC_OFFSET			8

#define MSS_PDC_MASK			BIT(MSS_PDC_OFFSET)



/* Timeout value for MBA boot when minidump is enabled */

#define MBA_ENCRYPTION_TIMEOUT	3000

enum scm_cmd {
@@ -214,13 +211,14 @@ static void pil_mss_disable_clks(struct q6v5_data *drv) 
static void pil_mss_pdc_sync(struct q6v5_data *drv, bool pdc_sync)

{

	u32 val = 0;

	u32 mss_pdc_mask = BIT(drv->mss_pdc_offset);



	if (drv->pdc_sync) {

		val = readl_relaxed(drv->pdc_sync);

		if (pdc_sync)

			val |= MSS_PDC_MASK;

			val |= mss_pdc_mask;

		else

			val &= ~MSS_PDC_MASK;

			val &= ~mss_pdc_mask;

		writel_relaxed(val, drv->pdc_sync);

		/* Ensure PDC is written before next write */

		wmb();