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Commit 506c07fc authored by Kyle Yan's avatar Kyle Yan
Browse files

soc: qcom: pil: Take MSS PDC offset from DT



As the offset for MSS PDC can change, mandate that the offset must be
specified by the DT instead of hardcoding the offset.

Change-Id: I486b496c082bc4a78d7a96087204870970d4ac89
Signed-off-by: default avatarKyle Yan <kyan@codeaurora.org>
parent f248e35f
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+3 −5
Original line number Diff line number Diff line
@@ -77,9 +77,6 @@

#define MSS_MAGIC			0XAABADEAD

#define MSS_PDC_OFFSET			8
#define MSS_PDC_MASK			BIT(MSS_PDC_OFFSET)

/* Timeout value for MBA boot when minidump is enabled */
#define MBA_ENCRYPTION_TIMEOUT	3000
enum scm_cmd {
@@ -214,13 +211,14 @@ static void pil_mss_disable_clks(struct q6v5_data *drv)
static void pil_mss_pdc_sync(struct q6v5_data *drv, bool pdc_sync)
{
	u32 val = 0;
	u32 mss_pdc_mask = BIT(drv->mss_pdc_offset);

	if (drv->pdc_sync) {
		val = readl_relaxed(drv->pdc_sync);
		if (pdc_sync)
			val |= MSS_PDC_MASK;
			val |= mss_pdc_mask;
		else
			val &= ~MSS_PDC_MASK;
			val &= ~mss_pdc_mask;
		writel_relaxed(val, drv->pdc_sync);
		/* Ensure PDC is written before next write */
		wmb();
+7 −0
Original line number Diff line number Diff line
@@ -293,6 +293,13 @@ static int pil_mss_loadable_init(struct modem_data *drv,
	if (res) {
		q6->pdc_sync = devm_ioremap(&pdev->dev,
						res->start, resource_size(res));
		if (of_property_read_u32(pdev->dev.of_node,
			"qcom,mss_pdc_offset", &q6->mss_pdc_offset)) {
			dev_err(&pdev->dev,
				"Offset for MSS PDC not specified\n");
			return -EINVAL;
		}

	}

	q6->alt_reset = NULL;
+1 −0
Original line number Diff line number Diff line
@@ -74,6 +74,7 @@ struct q6v5_data {
	bool restart_reg_sec;
	bool override_acc;
	int override_acc_1;
	int mss_pdc_offset;
	bool ahb_clk_vote;
	bool mx_spike_wa;
};