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Commit 627eb5a3 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: hw state readout support for pipe_config->fdi_lanes 



v2: Introduce some nice #defines for the FDI lane width fields and put
them to good use. Suggested by Ville.

v3: Fixup the mask vs. shift copy&pasta fail Imre Deak spotted, and
use the shift #define also in the mask.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 33d29b14

drivers/gpu/drm/i915/i915_reg.h

+3 −8
Original line number Diff line number Diff line
@@ -4146,10 +4146,9 @@ 
#define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39<<22)

#define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38<<22)

#define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f<<22)

#define  FDI_DP_PORT_WIDTH_X1           (0<<19)

#define  FDI_DP_PORT_WIDTH_X2           (1<<19)

#define  FDI_DP_PORT_WIDTH_X3           (2<<19)

#define  FDI_DP_PORT_WIDTH_X4           (3<<19)

#define  FDI_DP_PORT_WIDTH_SHIFT		19

#define  FDI_DP_PORT_WIDTH_MASK			(7 << FDI_DP_PORT_WIDTH_SHIFT)

#define  FDI_DP_PORT_WIDTH(width)           (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)

#define  FDI_TX_ENHANCE_FRAME_ENABLE    (1<<18)

/* Ironlake: hardwired to 1 */

#define  FDI_TX_PLL_ENABLE              (1<<14)
@@ -4174,7 +4173,6 @@ 
/* train, dp width same as FDI_TX */

#define  FDI_FS_ERRC_ENABLE		(1<<27)

#define  FDI_FE_ERRC_ENABLE		(1<<26)

#define  FDI_DP_PORT_WIDTH_X8           (7<<19)

#define  FDI_RX_POLARITY_REVERSED_LPT	(1<<16)

#define  FDI_8BPC                       (0<<16)

#define  FDI_10BPC                      (1<<16)
@@ -4196,9 +4194,6 @@ 
#define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2<<8)

#define  FDI_LINK_TRAIN_NORMAL_CPT		(3<<8)

#define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3<<8)

/* LPT */

#define  FDI_PORT_WIDTH_2X_LPT			(1<<19)

#define  FDI_PORT_WIDTH_1X_LPT			(0<<19)



#define _FDI_RXA_MISC			0xf0010

#define _FDI_RXB_MISC			0xf1010

drivers/gpu/drm/i915/intel_ddi.c

+1 −1
Original line number Diff line number Diff line
@@ -182,7 +182,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) 
	/* Enable the PCH Receiver FDI PLL */

	rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |

		     FDI_RX_PLL_ENABLE |

		     ((intel_crtc->config.fdi_lanes - 1) << 19);

		     FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);

	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);

	POSTING_READ(_FDI_RXA_CTL);

	udelay(220);

drivers/gpu/drm/i915/intel_display.c

+28 −10
Original line number Diff line number Diff line
@@ -2419,8 +2419,8 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc) 
	/* enable CPU FDI TX and PCH FDI RX */

	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	temp &= ~(7 << 19);

	temp |= (intel_crtc->config.fdi_lanes - 1) << 19;

	temp &= ~FDI_DP_PORT_WIDTH_MASK;

	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);

	temp &= ~FDI_LINK_TRAIN_NONE;

	temp |= FDI_LINK_TRAIN_PATTERN_1;

	I915_WRITE(reg, temp | FDI_TX_ENABLE);
@@ -2517,8 +2517,8 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc) 
	/* enable CPU FDI TX and PCH FDI RX */

	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	temp &= ~(7 << 19);

	temp |= (intel_crtc->config.fdi_lanes - 1) << 19;

	temp &= ~FDI_DP_PORT_WIDTH_MASK;

	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);

	temp &= ~FDI_LINK_TRAIN_NONE;

	temp |= FDI_LINK_TRAIN_PATTERN_1;

	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
@@ -2652,8 +2652,8 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) 
	/* enable CPU FDI TX and PCH FDI RX */

	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	temp &= ~(7 << 19);

	temp |= (intel_crtc->config.fdi_lanes - 1) << 19;

	temp &= ~FDI_DP_PORT_WIDTH_MASK;

	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);

	temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);

	temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;

	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
@@ -2754,8 +2754,8 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) 
	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */

	reg = FDI_RX_CTL(pipe);

	temp = I915_READ(reg);

	temp &= ~((0x7 << 19) | (0x7 << 16));

	temp |= (intel_crtc->config.fdi_lanes - 1) << 19;

	temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));

	temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);

	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;

	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
@@ -5784,9 +5784,14 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, 
	if (!(tmp & PIPECONF_ENABLE))

		return false;



	if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)

	if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {

		pipe_config->has_pch_encoder = true;



		tmp = I915_READ(FDI_RX_CTL(crtc->pipe));

		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>

					  FDI_DP_PORT_WIDTH_SHIFT) + 1;

	}



	return true;

}
@@ -5922,9 +5927,14 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, 
	 */

	tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));

	if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&

	    I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)

	    I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE) {

		pipe_config->has_pch_encoder = true;



		tmp = I915_READ(FDI_RX_CTL(PIPE_A));

		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>

					  FDI_DP_PORT_WIDTH_SHIFT) + 1;

	}



	return true;

}
@@ -7886,6 +7896,14 @@ intel_pipe_config_compare(struct intel_crtc_config *current_config, 
		return false;

	}



	if (current_config->fdi_lanes != pipe_config->fdi_lanes) {

		DRM_ERROR("mismatch in fdi_lanes "

			  "(expected %i, found %i)\n",

			  current_config->fdi_lanes,

			  pipe_config->fdi_lanes);

		return false;

	}



	return true;

}