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Commit 33d29b14 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: move intel_crtc->fdi_lanes to pipe_config 



We need this for two reasons:
- Correct handling of shared fdi lanes on ivb with fastboot.
- Handling fdi link bw limits when we only have two fdi lanes by
  dithering down a bit.

Just search&replace in this patch, no functional change at all.

Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 52541e30

drivers/gpu/drm/i915/intel_ddi.c

+4 −3
Original line number Diff line number Diff line
@@ -181,7 +181,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) 


	/* Enable the PCH Receiver FDI PLL */

	rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |

		     FDI_RX_PLL_ENABLE | ((intel_crtc->fdi_lanes - 1) << 19);

		     FDI_RX_PLL_ENABLE |

		     ((intel_crtc->config.fdi_lanes - 1) << 19);

	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);

	POSTING_READ(_FDI_RXA_CTL);

	udelay(220);
@@ -209,7 +210,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) 
		 * port reversal bit */

		I915_WRITE(DDI_BUF_CTL(PORT_E),

			   DDI_BUF_CTL_ENABLE |

			   ((intel_crtc->fdi_lanes - 1) << 1) |

			   ((intel_crtc->config.fdi_lanes - 1) << 1) |

			   hsw_ddi_buf_ctl_values[i / 2]);

		POSTING_READ(DDI_BUF_CTL(PORT_E));
@@ -1022,7 +1023,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) 


	} else if (type == INTEL_OUTPUT_ANALOG) {

		temp |= TRANS_DDI_MODE_SELECT_FDI;

		temp |= (intel_crtc->fdi_lanes - 1) << 1;

		temp |= (intel_crtc->config.fdi_lanes - 1) << 1;



	} else if (type == INTEL_OUTPUT_DISPLAYPORT ||

		   type == INTEL_OUTPUT_EDP) {

drivers/gpu/drm/i915/intel_display.c

+18 −18
Original line number Diff line number Diff line
@@ -2420,7 +2420,7 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc) 
	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	temp &= ~(7 << 19);

	temp |= (intel_crtc->fdi_lanes - 1) << 19;

	temp |= (intel_crtc->config.fdi_lanes - 1) << 19;

	temp &= ~FDI_LINK_TRAIN_NONE;

	temp |= FDI_LINK_TRAIN_PATTERN_1;

	I915_WRITE(reg, temp | FDI_TX_ENABLE);
@@ -2518,7 +2518,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc) 
	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	temp &= ~(7 << 19);

	temp |= (intel_crtc->fdi_lanes - 1) << 19;

	temp |= (intel_crtc->config.fdi_lanes - 1) << 19;

	temp &= ~FDI_LINK_TRAIN_NONE;

	temp |= FDI_LINK_TRAIN_PATTERN_1;

	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
@@ -2653,7 +2653,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) 
	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	temp &= ~(7 << 19);

	temp |= (intel_crtc->fdi_lanes - 1) << 19;

	temp |= (intel_crtc->config.fdi_lanes - 1) << 19;

	temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);

	temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;

	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
@@ -2755,7 +2755,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) 
	reg = FDI_RX_CTL(pipe);

	temp = I915_READ(reg);

	temp &= ~((0x7 << 19) | (0x7 << 16));

	temp |= (intel_crtc->fdi_lanes - 1) << 19;

	temp |= (intel_crtc->config.fdi_lanes - 1) << 19;

	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;

	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
@@ -5398,12 +5398,12 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc) 
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);



	DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",

		      pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);

	if (intel_crtc->fdi_lanes > 4) {

		      pipe_name(intel_crtc->pipe), intel_crtc->config.fdi_lanes);

	if (intel_crtc->config.fdi_lanes > 4) {

		DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",

			      pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);

			      pipe_name(intel_crtc->pipe), intel_crtc->config.fdi_lanes);

		/* Clamp lanes to avoid programming the hw with bogus values. */

		intel_crtc->fdi_lanes = 4;

		intel_crtc->config.fdi_lanes = 4;



		return false;

	}
@@ -5416,28 +5416,28 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc) 
		return true;

	case PIPE_B:

		if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&

		    intel_crtc->fdi_lanes > 2) {

		    intel_crtc->config.fdi_lanes > 2) {

			DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",

				      pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);

				      pipe_name(intel_crtc->pipe), intel_crtc->config.fdi_lanes);

			/* Clamp lanes to avoid programming the hw with bogus values. */

			intel_crtc->fdi_lanes = 2;

			intel_crtc->config.fdi_lanes = 2;



			return false;

		}



		if (intel_crtc->fdi_lanes > 2)

		if (intel_crtc->config.fdi_lanes > 2)

			WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);

		else

			cpt_enable_fdi_bc_bifurcation(dev);



		return true;

	case PIPE_C:

		if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {

			if (intel_crtc->fdi_lanes > 2) {

		if (!pipe_B_crtc->base.enabled || pipe_B_crtc->config.fdi_lanes <= 2) {

			if (intel_crtc->config.fdi_lanes > 2) {

				DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",

					      pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);

					      pipe_name(intel_crtc->pipe), intel_crtc->config.fdi_lanes);

				/* Clamp lanes to avoid programming the hw with bogus values. */

				intel_crtc->fdi_lanes = 2;

				intel_crtc->config.fdi_lanes = 2;



				return false;

			}
@@ -5525,7 +5525,7 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc) 
	lane = ironlake_get_lanes_required(target_clock, link_bw,

					   intel_crtc->config.pipe_bpp);



	intel_crtc->fdi_lanes = lane;

	intel_crtc->config.fdi_lanes = lane;



	if (intel_crtc->config.pixel_multiplier > 1)

		link_bw *= intel_crtc->config.pixel_multiplier;
@@ -5752,7 +5752,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 


	/* Note, this also computes intel_crtc->fdi_lanes which is used below in

	 * ironlake_check_fdi_lanes. */

	intel_crtc->fdi_lanes = 0;

	intel_crtc->config.fdi_lanes = 0;

	if (intel_crtc->config.has_pch_encoder)

		ironlake_fdi_set_m_n(crtc);

drivers/gpu/drm/i915/intel_drv.h

+3 −1
Original line number Diff line number Diff line
@@ -249,6 +249,9 @@ struct intel_crtc_config { 
		u32 pos;

		u32 size;

	} pch_pfit;



	/* FDI lanes used, only valid if has_pch_encoder is set. */

	int fdi_lanes;

};



struct intel_crtc {
@@ -267,7 +270,6 @@ struct intel_crtc { 
	bool lowfreq_avail;

	struct intel_overlay *overlay;

	struct intel_unpin_work *unpin_work;

	int fdi_lanes;



	atomic_t unpin_work_count;