clk: msm: mdss: fix DP register configurations

This change provides the below updates:

- Current DP PLL driver uses the pll_base and the base
  address for the TXn registers instead of phy_base address.
  Fix this by using the correct base address.

- Disable handoff for vco_divided_clk
  by implementing handoff function for this clock.

- Update the PLL settings to fix PLL locking issues.

CRs-Fixed: 1009740
Change-Id: Iea46c5b0482bceb841309175ede42ec3be3e20fd
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>