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Commit 56611efa authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru Committed by Gerrit - the friendly Code Review server
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drm: msm: dsi-staging: add support for DSI PHY v3.0 



Add support for DSI PHY h/w driver for DSI PHY v3.0 which
is present on msm8998. This includes reorganising the DSI
PHY timing calculation logic which is common between DSI
PHY v2.0 and v3.0.

CRs-Fixed: 2008002
Change-Id: I789cf1d618a0dd27935f38438af7dde35810e80f
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: default avatarShashank Babu Chinta Venkata <sbchin@codeaurora.org>
parent 8ee8ee52

Documentation/devicetree/bindings/drm/msm/sde-dsi.txt

+4 −3
Original line number Diff line number Diff line
@@ -9,8 +9,9 @@ Required properties: 
			versions include 1.4 and 2.0.

			eg: qcom,dsi-ctrl-hw-v1.4, qcom,dsi-ctrl-hw-v2.0

			And for dsi phy driver:

			qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0, qcom,dsi-phy-v3.0,

			qcom,dsi-phy-v4.0

			qcom,dsi-phy-v0.0-hpm, qcom,dsi-phy-v0.0-lpm,

			qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0,

			qcom,dsi-phy-v3.0

- reg:                  Base address and length of DSI controller's memory

			mapped regions.

- reg-names:            A list of strings that name the list of regs.

drivers/gpu/drm/msm/Makefile

+5 −1
Original line number Diff line number Diff line
@@ -97,7 +97,11 @@ endif 
msm_drm-$(CONFIG_DRM_MSM_DSI_STAGING) += dsi-staging/dsi_phy.o \

				dsi-staging/dsi_pwr.o \

				dsi-staging/dsi_phy.o \

				dsi-staging/dsi_phy_hw_v4_0.o \

				dsi-staging/dsi_phy_hw_v2_0.o \

				dsi-staging/dsi_phy_hw_v3_0.o \

				dsi-staging/dsi_phy_timing_calc.o \

				dsi-staging/dsi_phy_timing_v2_0.o \

				dsi-staging/dsi_phy_timing_v3_0.o \

				dsi-staging/dsi_ctrl_hw_cmn.o \

				dsi-staging/dsi_ctrl_hw_1_4.o \

				dsi-staging/dsi_ctrl_hw_2_0.o \

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c

+41 −13
Original line number Diff line number Diff line
@@ -131,18 +131,41 @@ int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl, 
}



/**

 * dsi_catalog_phy_4_0_init() - catalog init for DSI PHY v4.0

 * dsi_catalog_phy_2_0_init() - catalog init for DSI PHY 14nm

 */

static void dsi_catalog_phy_4_0_init(struct dsi_phy_hw *phy)

static void dsi_catalog_phy_2_0_init(struct dsi_phy_hw *phy)

{

	phy->ops.regulator_enable = dsi_phy_hw_v4_0_regulator_enable;

	phy->ops.regulator_disable = dsi_phy_hw_v4_0_regulator_disable;

	phy->ops.enable = dsi_phy_hw_v4_0_enable;

	phy->ops.disable = dsi_phy_hw_v4_0_disable;

	phy->ops.regulator_enable = dsi_phy_hw_v2_0_regulator_enable;

	phy->ops.regulator_disable = dsi_phy_hw_v2_0_regulator_disable;

	phy->ops.enable = dsi_phy_hw_v2_0_enable;

	phy->ops.disable = dsi_phy_hw_v2_0_disable;

	phy->ops.calculate_timing_params =

		dsi_phy_hw_v4_0_calculate_timing_params;

	phy->ops.phy_idle_on = dsi_phy_hw_v4_0_idle_on;

	phy->ops.phy_idle_off = dsi_phy_hw_v4_0_idle_off;

		dsi_phy_hw_calculate_timing_params;

	phy->ops.phy_idle_on = dsi_phy_hw_v2_0_idle_on;

	phy->ops.phy_idle_off = dsi_phy_hw_v2_0_idle_off;

	phy->ops.calculate_timing_params =

		dsi_phy_hw_calculate_timing_params;

}



/**

 * dsi_catalog_phy_3_0_init() - catalog init for DSI PHY 10nm

 */

static void dsi_catalog_phy_3_0_init(struct dsi_phy_hw *phy)

{

	phy->ops.regulator_enable = dsi_phy_hw_v3_0_regulator_enable;

	phy->ops.regulator_disable = dsi_phy_hw_v3_0_regulator_disable;

	phy->ops.enable = dsi_phy_hw_v3_0_enable;

	phy->ops.disable = dsi_phy_hw_v3_0_disable;

	phy->ops.calculate_timing_params =

		dsi_phy_hw_calculate_timing_params;

	phy->ops.ulps_ops.wait_for_lane_idle =

		dsi_phy_hw_v3_0_wait_for_lane_idle;

	phy->ops.ulps_ops.ulps_request =

		dsi_phy_hw_v3_0_ulps_request;

	phy->ops.ulps_ops.ulps_exit =

		dsi_phy_hw_v3_0_ulps_exit;

	phy->ops.ulps_ops.get_lanes_in_ulps =

		dsi_phy_hw_v3_0_get_lanes_in_ulps;

}



/**
@@ -170,13 +193,18 @@ int dsi_catalog_phy_setup(struct dsi_phy_hw *phy, 
	phy->index = index;

	set_bit(DSI_PHY_DPHY, phy->feature_map);



	dsi_phy_timing_calc_init(phy, version);



	switch (version) {

	case DSI_PHY_VERSION_4_0:

		dsi_catalog_phy_4_0_init(phy);

		break;

	case DSI_PHY_VERSION_1_0:

	case DSI_PHY_VERSION_2_0:

		dsi_catalog_phy_2_0_init(phy);

		break;

	case DSI_PHY_VERSION_3_0:

		dsi_catalog_phy_3_0_init(phy);

		break;

	case DSI_PHY_VERSION_0_0_HPM:

	case DSI_PHY_VERSION_0_0_LPM:

	case DSI_PHY_VERSION_1_0:

	default:

		return -ENOTSUPP;

	}

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h

+48 −13
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl, 


/**

 * dsi_catalog_phy_setup() - return catalog info for dsi phy hardware

 * @ctrl:        Pointer to DSI PHY hw object.

 * @phy:        Pointer to DSI PHY hw object.

 * @version:     DSI PHY version.

 * @index:       DSI PHY instance ID.

 *
@@ -46,20 +46,55 @@ int dsi_catalog_phy_setup(struct dsi_phy_hw *phy, 
			  enum dsi_phy_version version,

			  u32 index);



/* Definitions for 4.0 PHY hardware driver */

void dsi_phy_hw_v4_0_regulator_enable(struct dsi_phy_hw *phy,

				      struct dsi_phy_per_lane_cfgs *cfg);

void dsi_phy_hw_v4_0_regulator_disable(struct dsi_phy_hw *phy);

void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);

void dsi_phy_hw_v4_0_disable(struct dsi_phy_hw *phy);

int dsi_phy_hw_v4_0_calculate_timing_params(struct dsi_phy_hw *phy,

/**

 * dsi_phy_timing_calc_init() - initialize info for DSI PHY timing calculations

 * @phy:        Pointer to DSI PHY hw object.

 * @version:     DSI PHY version.

 *

 * This function setups the catalog information in the dsi_phy_hw object.

 *

 * return: error code for failure and 0 for success.

 */

int dsi_phy_timing_calc_init(struct dsi_phy_hw *phy,

	enum dsi_phy_version version);



/**

 * dsi_phy_hw_calculate_timing_params() - DSI PHY timing parameter calculations

 * @phy:        Pointer to DSI PHY hw object.

 * @mode:       DSI mode information.

 * @host:       DSI host configuration.

 * @timing:     DSI phy lane configurations.

 *

 * This function setups the catalog information in the dsi_phy_hw object.

 *

 * return: error code for failure and 0 for success.

 */

int dsi_phy_hw_calculate_timing_params(struct dsi_phy_hw *phy,

					    struct dsi_mode_info *mode,

					    struct dsi_host_common_cfg *cfg,

					   struct dsi_phy_per_lane_cfgs

					   *timing);

void dsi_phy_hw_v4_0_idle_on(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);

void dsi_phy_hw_v4_0_idle_off(struct dsi_phy_hw *phy);

	struct dsi_host_common_cfg *host,

	struct dsi_phy_per_lane_cfgs *timing);



/* Definitions for 14nm PHY hardware driver */

void dsi_phy_hw_v2_0_regulator_enable(struct dsi_phy_hw *phy,

				      struct dsi_phy_per_lane_cfgs *cfg);

void dsi_phy_hw_v2_0_regulator_disable(struct dsi_phy_hw *phy);

void dsi_phy_hw_v2_0_enable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);

void dsi_phy_hw_v2_0_disable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);

void dsi_phy_hw_v2_0_idle_on(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);

void dsi_phy_hw_v2_0_idle_off(struct dsi_phy_hw *phy);



/* Definitions for 10nm PHY hardware driver */

void dsi_phy_hw_v3_0_regulator_enable(struct dsi_phy_hw *phy,

				      struct dsi_phy_per_lane_cfgs *cfg);

void dsi_phy_hw_v3_0_regulator_disable(struct dsi_phy_hw *phy);

void dsi_phy_hw_v3_0_enable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);

void dsi_phy_hw_v3_0_disable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);

int dsi_phy_hw_v3_0_wait_for_lane_idle(struct dsi_phy_hw *phy, u32 lanes);

void dsi_phy_hw_v3_0_ulps_request(struct dsi_phy_hw *phy,

		struct dsi_phy_cfg *cfg, u32 lanes);

void dsi_phy_hw_v3_0_ulps_exit(struct dsi_phy_hw *phy,

			struct dsi_phy_cfg *cfg, u32 lanes);

u32 dsi_phy_hw_v3_0_get_lanes_in_ulps(struct dsi_phy_hw *phy);

/* DSI controller common ops */

u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl);

void dsi_ctrl_hw_cmn_clear_interrupt_status(struct dsi_ctrl_hw *ctrl, u32 ints);

drivers/gpu/drm/msm/dsi-staging/dsi_display.c

+13 −0
Original line number Diff line number Diff line
@@ -236,6 +236,12 @@ static int dsi_display_set_ulps(struct dsi_display *display, bool enable) 
		return rc;

	}



	rc = dsi_phy_set_ulps(m_ctrl->phy, &display->config, enable);

	if (rc) {

		pr_err("Ulps PHY state change(%d) failed\n", enable);

		return rc;

	}



	for (i = 0; i < display->ctrl_count; i++) {

		ctrl = &display->ctrl[i];

		if (!ctrl->ctrl || (ctrl == m_ctrl))
@@ -247,6 +253,13 @@ static int dsi_display_set_ulps(struct dsi_display *display, bool enable) 
				enable);

			return rc;

		}



		rc = dsi_phy_set_ulps(ctrl->phy, &display->config, enable);

		if (rc) {

			pr_err("Ulps PHY state change(%d) failed\n", enable);

			return rc;

		}



	}

	display->ulps_enabled = enable;

	return 0;