Merge "ARM: dts: msm: Add aggregate ufs phy axi clock for sdhc1 in sdm670"

		clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,

			<&clock_gcc GCC_SDCC1_APPS_CLK>,

			<&clock_gcc GCC_SDCC1_ICE_CORE_CLK>;

		clock-names = "iface_clk", "core_clk", "ice_core_clk";

			<&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,

			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;

		clock-names = "iface_clk", "core_clk", "ice_core_clk",

			"bus_aggr_clk";

		qcom,ice-clk-rates = <300000000 75000000>;