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Commit 7e20ddce authored by Vijay Viswanath's avatar Vijay Viswanath
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ARM: dts: msm: Add aggregate ufs phy axi clock for sdhc1 in sdm670 



Sdhc1 controller in sdm670 require gcc_aggre_ufs_phy_axi_clk to be on
for ADMA to work. eMMC controller (sdhc1) requires this because, in
sdm670, the sdhc1 and ufs controllers share a common data path and the
common path uses the ufs_phy_axi clock. The use of UFS clock was
continued for the common path because of HW design considerations.

Change-Id: Ia09889228c73370278805a8e05c248ae21d8cd3a
Signed-off-by: default avatarVijay Viswanath <vviswana@codeaurora.org>
parent 755735e7

arch/arm64/boot/dts/qcom/sdm670.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -2198,8 +2198,10 @@ 


		clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,

			<&clock_gcc GCC_SDCC1_APPS_CLK>,

			<&clock_gcc GCC_SDCC1_ICE_CORE_CLK>;

		clock-names = "iface_clk", "core_clk", "ice_core_clk";

			<&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,

			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;

		clock-names = "iface_clk", "core_clk", "ice_core_clk",

			"bus_aggr_clk";



		qcom,ice-clk-rates = <300000000 75000000>;