Loading drivers/gpu/msm/adreno_a6xx.c +21 −21 Original line number Diff line number Diff line Loading @@ -73,14 +73,14 @@ static const struct kgsl_hwcg_reg a630_hwcg_regs[] = { {A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220}, {A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220}, {A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220}, {A6XX_RBBM_CLOCK_DELAY_SP0, 0x0000F3CF}, {A6XX_RBBM_CLOCK_DELAY_SP1, 0x0000F3CF}, {A6XX_RBBM_CLOCK_DELAY_SP2, 0x0000F3CF}, {A6XX_RBBM_CLOCK_DELAY_SP3, 0x0000F3CF}, {A6XX_RBBM_CLOCK_HYST_SP0, 0x00000080}, {A6XX_RBBM_CLOCK_HYST_SP1, 0x00000080}, {A6XX_RBBM_CLOCK_HYST_SP2, 0x00000080}, {A6XX_RBBM_CLOCK_HYST_SP3, 0x00000080}, {A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, {A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, {A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080}, {A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080}, {A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, {A6XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF}, {A6XX_RBBM_CLOCK_HYST_SP2, 0x0000F3CF}, {A6XX_RBBM_CLOCK_HYST_SP3, 0x0000F3CF}, {A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, {A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, {A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222}, Loading @@ -105,10 +105,10 @@ static const struct kgsl_hwcg_reg a630_hwcg_regs[] = { {A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, {A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777}, {A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777}, {A6XX_RBBM_CLOCK_HYST3_TP0, 0x07777777}, {A6XX_RBBM_CLOCK_HYST3_TP1, 0x07777777}, {A6XX_RBBM_CLOCK_HYST3_TP2, 0x07777777}, {A6XX_RBBM_CLOCK_HYST3_TP3, 0x07777777}, {A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, {A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, {A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777}, {A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777}, {A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, {A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, {A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777}, Loading Loading @@ -143,20 +143,20 @@ static const struct kgsl_hwcg_reg a630_hwcg_regs[] = { {A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222}, {A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222}, {A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222}, {A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00000000}, {A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00000000}, {A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00000000}, {A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00000000}, {A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, {A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, {A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, {A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, {A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, {A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00}, {A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00}, {A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00}, {A6XX_RBBM_CLOCK_CNTL_RAC, 0x00022022}, {A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005550}, {A6XX_RBBM_CLOCK_DELAY_RAC, 0x00010011}, {A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, {A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, {A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, {A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, {A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222220}, {A6XX_RBBM_CLOCK_MODE_GPC, 0x00202222}, {A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, {A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, {A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, {A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, {A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, Loading Loading
drivers/gpu/msm/adreno_a6xx.c +21 −21 Original line number Diff line number Diff line Loading @@ -73,14 +73,14 @@ static const struct kgsl_hwcg_reg a630_hwcg_regs[] = { {A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220}, {A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220}, {A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220}, {A6XX_RBBM_CLOCK_DELAY_SP0, 0x0000F3CF}, {A6XX_RBBM_CLOCK_DELAY_SP1, 0x0000F3CF}, {A6XX_RBBM_CLOCK_DELAY_SP2, 0x0000F3CF}, {A6XX_RBBM_CLOCK_DELAY_SP3, 0x0000F3CF}, {A6XX_RBBM_CLOCK_HYST_SP0, 0x00000080}, {A6XX_RBBM_CLOCK_HYST_SP1, 0x00000080}, {A6XX_RBBM_CLOCK_HYST_SP2, 0x00000080}, {A6XX_RBBM_CLOCK_HYST_SP3, 0x00000080}, {A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, {A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, {A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080}, {A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080}, {A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, {A6XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF}, {A6XX_RBBM_CLOCK_HYST_SP2, 0x0000F3CF}, {A6XX_RBBM_CLOCK_HYST_SP3, 0x0000F3CF}, {A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, {A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, {A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222}, Loading @@ -105,10 +105,10 @@ static const struct kgsl_hwcg_reg a630_hwcg_regs[] = { {A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, {A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777}, {A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777}, {A6XX_RBBM_CLOCK_HYST3_TP0, 0x07777777}, {A6XX_RBBM_CLOCK_HYST3_TP1, 0x07777777}, {A6XX_RBBM_CLOCK_HYST3_TP2, 0x07777777}, {A6XX_RBBM_CLOCK_HYST3_TP3, 0x07777777}, {A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, {A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, {A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777}, {A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777}, {A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, {A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, {A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777}, Loading Loading @@ -143,20 +143,20 @@ static const struct kgsl_hwcg_reg a630_hwcg_regs[] = { {A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222}, {A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222}, {A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222}, {A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00000000}, {A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00000000}, {A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00000000}, {A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00000000}, {A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, {A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, {A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, {A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, {A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, {A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00}, {A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00}, {A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00}, {A6XX_RBBM_CLOCK_CNTL_RAC, 0x00022022}, {A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005550}, {A6XX_RBBM_CLOCK_DELAY_RAC, 0x00010011}, {A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, {A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, {A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, {A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, {A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222220}, {A6XX_RBBM_CLOCK_MODE_GPC, 0x00202222}, {A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, {A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, {A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, {A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, {A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, Loading