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Commit 4c8f2d60 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "Revert "clk: msm: mdss: read pre-calibrated PLL codes from dfps memory""

parents ad699306 230b7fbe

drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c

+1 −54
Original line number Diff line number Diff line
@@ -53,52 +53,6 @@ int get_mdss_pixel_mux_sel_8996(struct mux_clk *clk) 
	return 0;

}



static int mdss_pll_read_stored_trim_codes(

		struct mdss_pll_resources *dsi_pll_res, s64 vco_clk_rate,

		int *pll_trim_codes)

{

	int i;

	int rc = 0;

	bool found = false;



	if (!dsi_pll_res->dfps) {

		rc = -EINVAL;

		goto end_read;

	}



	for (i = 0; i < dsi_pll_res->dfps->panel_dfps.frame_rate_cnt; i++) {

		struct dfps_codes_info *codes_info =

			&dsi_pll_res->dfps->codes_dfps[i];



		pr_debug("valid=%d frame_rate=%d, vco_rate=%d, code %d %d\n",

			codes_info->is_valid, codes_info->frame_rate,

			codes_info->clk_rate, codes_info->pll_codes.pll_codes_1,

			codes_info->pll_codes.pll_codes_2);



		if (vco_clk_rate != codes_info->clk_rate &&

				codes_info->is_valid)

			continue;



		pll_trim_codes[0] =

			codes_info->pll_codes.pll_codes_1;

		pll_trim_codes[1] =

			codes_info->pll_codes.pll_codes_2;

		found = true;

		break;

	}



	if (!found) {

		rc = -EINVAL;

		goto end_read;

	}



	pr_debug("core_kvco_code=0x%x core_vco_tune=0x%x\n",

			pll_trim_codes[0], pll_trim_codes[1]);



end_read:

	return rc;

}



int post_n1_div_set_div(struct div_clk *clk, int div)

{

	struct mdss_pll_resources *pll = clk->priv;
@@ -1091,8 +1045,7 @@ int shadow_pll_vco_set_rate_8996(struct clk *c, unsigned long rate) 
	struct dsi_pll_vco_clk *vco = to_vco_clk(c);

	struct mdss_pll_resources *pll = vco->priv;

	struct dsi_pll_db *pdb;

	s64 vco_clk_rate = (s64)rate;

	int pll_trim_codes[2];

	int pll_trim_codes[2] = {0, 0};



	if (!pll) {

		pr_err("PLL data not found\n");
@@ -1105,12 +1058,6 @@ int shadow_pll_vco_set_rate_8996(struct clk *c, unsigned long rate) 
		return -EINVAL;

	}



	rc = mdss_pll_read_stored_trim_codes(pll, vco_clk_rate, pll_trim_codes);

	if (rc) {

		pr_err("cannot find pll codes rate=%lld\n", vco_clk_rate);

		return -EINVAL;

	}



	rc = mdss_pll_resource_enable(pll, true);

	if (rc) {

		pr_err("Failed to enable mdss dsi plla=%d\n", pll->index);

drivers/clk/msm/mdss/mdss-pll-util.c

+0 −84
Original line number Diff line number Diff line
@@ -17,8 +17,6 @@ 
#include <linux/err.h>

#include <linux/string.h>

#include <linux/clk/msm-clock-generic.h>

#include <linux/of_address.h>

#include <linux/dma-mapping.h>

#include <linux/vmalloc.h>

#include <linux/memblock.h>
@@ -338,85 +336,6 @@ static int mdss_pll_util_parse_dt_clock(struct platform_device *pdev, 
	return rc;

}



static void mdss_pll_free_bootmem(u32 mem_addr, u32 size)

{

	unsigned long pfn_start, pfn_end, pfn_idx;



	pfn_start = mem_addr >> PAGE_SHIFT;

	pfn_end = (mem_addr + size) >> PAGE_SHIFT;

	for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)

		free_reserved_page(pfn_to_page(pfn_idx));

}



static int mdss_pll_util_parse_dt_dfps(struct platform_device *pdev,

					struct mdss_pll_resources *pll_res)

{

	int rc = 0;

	struct device_node *pnode;

	const u32 *addr;

	struct vm_struct *area;

	u64 size;

	u32 offsets[2];

	unsigned long virt_add;



	pnode = of_parse_phandle(pdev->dev.of_node, "memory-region", 0);

	if (IS_ERR_OR_NULL(pnode)) {

		rc = PTR_ERR(pnode);

		goto pnode_err;

	}



	addr = of_get_address(pnode, 0, &size, NULL);

	if (!addr) {

		pr_err("failed to parse the dfps memory address\n");

		rc = -EINVAL;

		goto pnode_err;

	}

	/* maintain compatibility for 32/64 bit */

	offsets[0] = (u32) of_read_ulong(addr, 2);

	offsets[1] = (u32) size;



	area = get_vm_area(offsets[1], VM_IOREMAP);

	if (!area) {

		rc = -ENOMEM;

		goto dfps_mem_err;

	}



	virt_add = (unsigned long)area->addr;

	rc = ioremap_page_range(virt_add, (virt_add + offsets[1]),

			offsets[0], PAGE_KERNEL);

	if (rc) {

		rc = -ENOMEM;

		goto ioremap_err;

	}



	pll_res->dfps = kzalloc(sizeof(struct dfps_info), GFP_KERNEL);

	if (IS_ERR_OR_NULL(pll_res->dfps)) {

		rc = PTR_ERR(pll_res->dfps);

		pr_err("couldn't allocate dfps kernel memory\n");

		goto addr_err;

	}



	/* memcopy complete dfps structure from kernel virtual memory */

	memcpy_fromio(pll_res->dfps, area->addr, sizeof(struct dfps_info));



addr_err:

	if (virt_add)

		unmap_kernel_range(virt_add, (unsigned long) size);

ioremap_err:

	if (area)

		vfree(area->addr);

dfps_mem_err:

	/* free the dfps memory here */

	memblock_free(offsets[0], offsets[1]);

	mdss_pll_free_bootmem(offsets[0], offsets[1]);

pnode_err:

	if (pnode)

		of_node_put(pnode);



	dma_release_declared_memory(&pdev->dev);

	return rc;

}



int mdss_pll_util_resource_parse(struct platform_device *pdev,

				struct mdss_pll_resources *pll_res)

{
@@ -435,9 +354,6 @@ int mdss_pll_util_resource_parse(struct platform_device *pdev, 
		goto clk_err;

	}



	if (mdss_pll_util_parse_dt_dfps(pdev, pll_res))

		pr_err("dfps not enabled!\n");



	return rc;



clk_err:

drivers/clk/msm/mdss/mdss-pll.h

+0 −27
Original line number Diff line number Diff line
@@ -46,33 +46,6 @@ enum { 
	MDSS_PLL_TARGET_8909,

};



#define DFPS_MAX_NUM_OF_FRAME_RATES 20



struct dfps_panel_info {

	uint32_t enabled;

	uint32_t frame_rate_cnt;

	uint32_t frame_rate[DFPS_MAX_NUM_OF_FRAME_RATES]; /* hz */

};



struct dfps_pll_codes {

	uint32_t pll_codes_1;

	uint32_t pll_codes_2;

};



struct dfps_codes_info {

	uint32_t is_valid;

	uint32_t frame_rate;	/* hz */

	uint32_t clk_rate;	/* hz */

	struct dfps_pll_codes pll_codes;

};



struct dfps_info {

	struct dfps_panel_info panel_dfps;

	struct dfps_codes_info codes_dfps[DFPS_MAX_NUM_OF_FRAME_RATES];

	void *dfps_fb_base;

	uint32_t chip_serial;

};



struct mdss_pll_resources {



	/* Pll specific resources like GPIO, power supply, clocks, etc*/