Loading drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c +1 −1 Original line number Diff line number Diff line Loading @@ -1141,7 +1141,7 @@ int shadow_pll_vco_set_rate_8996(struct clk *c, unsigned long rate) return rc; } unsigned long pll_vco_get_rate_8996(struct clk *c) static unsigned long pll_vco_get_rate_8996(struct clk *c) { u64 vco_rate, multiplier = BIT(20); s32 div_frac_start; Loading drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c +7 −7 Original line number Diff line number Diff line Loading @@ -31,14 +31,14 @@ #define HDMI_CLKS_PLL_DIVSEL 0 #define HDMI_CORECLK_DIV 5 #define HDMI_REF_CLOCK 19200000 #define HDMI_64B_ERR_VAL 0xFFFFFFFFFFFFFFFF #define HDMI_64B_ERR_VAL 0xFFFFFFFFFFFFFFFFULL #define HDMI_VERSION_8996_V1 1 #define HDMI_VERSION_8996_V2 2 #define HDMI_VERSION_8996_V3 3 #define HDMI_VERSION_8996_V3_1_8 4 #define HDMI_VCO_MAX_FREQ 12000000000 #define HDMI_VCO_MIN_FREQ 8000000000 #define HDMI_VCO_MAX_FREQ 12000000000UL #define HDMI_VCO_MIN_FREQ 8000000000UL #define HDMI_2400MHZ_BIT_CLK_HZ 2400000000UL #define HDMI_2250MHZ_BIT_CLK_HZ 2250000000UL #define HDMI_2000MHZ_BIT_CLK_HZ 2000000000UL Loading Loading @@ -2566,7 +2566,7 @@ static enum handoff hdmi_8996_vco_handoff(struct clk *c) return ret; } const struct clk_ops hdmi_8996_v1_vco_clk_ops = { static const struct clk_ops hdmi_8996_v1_vco_clk_ops = { .enable = hdmi_8996_v1_vco_enable, .set_rate = hdmi_8996_v1_vco_set_rate, .get_rate = hdmi_8996_vco_get_rate, Loading @@ -2576,7 +2576,7 @@ const struct clk_ops hdmi_8996_v1_vco_clk_ops = { .handoff = hdmi_8996_vco_handoff, }; const struct clk_ops hdmi_8996_v2_vco_clk_ops = { static const struct clk_ops hdmi_8996_v2_vco_clk_ops = { .enable = hdmi_8996_v2_vco_enable, .set_rate = hdmi_8996_v2_vco_set_rate, .get_rate = hdmi_8996_vco_get_rate, Loading @@ -2586,7 +2586,7 @@ const struct clk_ops hdmi_8996_v2_vco_clk_ops = { .handoff = hdmi_8996_vco_handoff, }; const struct clk_ops hdmi_8996_v3_vco_clk_ops = { static const struct clk_ops hdmi_8996_v3_vco_clk_ops = { .enable = hdmi_8996_v3_vco_enable, .set_rate = hdmi_8996_v3_vco_set_rate, .get_rate = hdmi_8996_vco_get_rate, Loading @@ -2596,7 +2596,7 @@ const struct clk_ops hdmi_8996_v3_vco_clk_ops = { .handoff = hdmi_8996_vco_handoff, }; const struct clk_ops hdmi_8996_v3_1p8_vco_clk_ops = { static const struct clk_ops hdmi_8996_v3_1p8_vco_clk_ops = { .enable = hdmi_8996_v3_1p8_vco_enable, .set_rate = hdmi_8996_v3_1p8_vco_set_rate, .get_rate = hdmi_8996_vco_get_rate, Loading drivers/clk/msm/mdss/mdss-pll-util.c +23 −22 Original line number Diff line number Diff line Loading @@ -28,16 +28,16 @@ int mdss_pll_util_resource_init(struct platform_device *pdev, struct mdss_pll_resources *pll_res) { int rc = 0; struct dss_module_power *mp = &pll_res->mp; struct mdss_module_power *mp = &pll_res->mp; rc = msm_dss_config_vreg(&pdev->dev, rc = msm_mdss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 1); if (rc) { pr_err("Vreg config failed rc=%d\n", rc); goto vreg_err; } rc = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk); rc = msm_mdss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk); if (rc) { pr_err("Clock get failed rc=%d\n", rc); goto clk_err; Loading @@ -46,7 +46,7 @@ int mdss_pll_util_resource_init(struct platform_device *pdev, return rc; clk_err: msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0); msm_mdss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0); vreg_err: return rc; } Loading @@ -59,11 +59,11 @@ int mdss_pll_util_resource_init(struct platform_device *pdev, * This is a helper function to retrieve the regulator information * for each pll resource. */ struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res struct mdss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res , char *name) { struct dss_vreg *regulator = NULL; struct mdss_vreg *regulator = NULL; int i; if ((pll_res == NULL) || (pll_res->mp.vreg_config == NULL)) { Loading @@ -88,17 +88,17 @@ struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res void mdss_pll_util_resource_deinit(struct platform_device *pdev, struct mdss_pll_resources *pll_res) { struct dss_module_power *mp = &pll_res->mp; struct mdss_module_power *mp = &pll_res->mp; msm_dss_put_clk(mp->clk_config, mp->num_clk); msm_mdss_put_clk(mp->clk_config, mp->num_clk); msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0); msm_mdss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0); } void mdss_pll_util_resource_release(struct platform_device *pdev, struct mdss_pll_resources *pll_res) { struct dss_module_power *mp = &pll_res->mp; struct mdss_module_power *mp = &pll_res->mp; devm_kfree(&pdev->dev, mp->clk_config); devm_kfree(&pdev->dev, mp->vreg_config); Loading @@ -110,36 +110,37 @@ int mdss_pll_util_resource_enable(struct mdss_pll_resources *pll_res, bool enable) { int rc = 0; struct dss_module_power *mp = &pll_res->mp; struct mdss_module_power *mp = &pll_res->mp; if (enable) { rc = msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable); rc = msm_mdss_enable_vreg(mp->vreg_config, mp->num_vreg, enable); if (rc) { pr_err("Failed to enable vregs rc=%d\n", rc); goto vreg_err; } rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk); rc = msm_mdss_clk_set_rate(mp->clk_config, mp->num_clk); if (rc) { pr_err("Failed to set clock rate rc=%d\n", rc); goto clk_err; } rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable); rc = msm_mdss_enable_clk(mp->clk_config, mp->num_clk, enable); if (rc) { pr_err("clock enable failed rc:%d\n", rc); goto clk_err; } } else { msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable); msm_mdss_enable_clk(mp->clk_config, mp->num_clk, enable); msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable); msm_mdss_enable_vreg(mp->vreg_config, mp->num_vreg, enable); } return rc; clk_err: msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, 0); msm_mdss_enable_vreg(mp->vreg_config, mp->num_vreg, 0); vreg_err: return rc; } Loading @@ -151,7 +152,7 @@ static int mdss_pll_util_parse_dt_supply(struct platform_device *pdev, u32 tmp = 0; struct device_node *of_node = NULL, *supply_root_node = NULL; struct device_node *supply_node = NULL; struct dss_module_power *mp = &pll_res->mp; struct mdss_module_power *mp = &pll_res->mp; of_node = pdev->dev.of_node; Loading @@ -173,7 +174,7 @@ static int mdss_pll_util_parse_dt_supply(struct platform_device *pdev, } pr_debug("vreg found. count=%d\n", mp->num_vreg); mp->vreg_config = devm_kzalloc(&pdev->dev, sizeof(struct dss_vreg) * mp->vreg_config = devm_kzalloc(&pdev->dev, sizeof(struct mdss_vreg) * mp->num_vreg, GFP_KERNEL); if (!mp->vreg_config) { rc = -ENOMEM; Loading Loading @@ -298,7 +299,7 @@ static int mdss_pll_util_parse_dt_clock(struct platform_device *pdev, struct mdss_pll_resources *pll_res) { u32 i = 0, rc = 0; struct dss_module_power *mp = &pll_res->mp; struct mdss_module_power *mp = &pll_res->mp; const char *clock_name; u32 clock_rate; Loading @@ -310,7 +311,7 @@ static int mdss_pll_util_parse_dt_clock(struct platform_device *pdev, } mp->clk_config = devm_kzalloc(&pdev->dev, sizeof(struct dss_clk) * mp->num_clk, GFP_KERNEL); sizeof(struct mdss_clk) * mp->num_clk, GFP_KERNEL); if (!mp->clk_config) { rc = -ENOMEM; mp->num_clk = 0; Loading Loading @@ -420,7 +421,7 @@ int mdss_pll_util_resource_parse(struct platform_device *pdev, struct mdss_pll_resources *pll_res) { int rc = 0; struct dss_module_power *mp = &pll_res->mp; struct mdss_module_power *mp = &pll_res->mp; rc = mdss_pll_util_parse_dt_supply(pdev, pll_res); if (rc) { Loading drivers/clk/msm/mdss/mdss-pll.h +3 −3 Original line number Diff line number Diff line /* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. /* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -76,7 +76,7 @@ struct dfps_info { struct mdss_pll_resources { /* Pll specific resources like GPIO, power supply, clocks, etc*/ struct dss_module_power mp; struct mdss_module_power mp; /* * dsi/edp/hmdi plls' base register, phy, gdsc and dynamic refresh Loading Loading @@ -219,6 +219,6 @@ int mdss_pll_util_resource_enable(struct mdss_pll_resources *pll_res, bool enable); int mdss_pll_util_resource_parse(struct platform_device *pdev, struct mdss_pll_resources *pll_res); struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res struct mdss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res , char *name); #endif drivers/video/fbdev/msm/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -21,6 +21,7 @@ mdss-mdp-objs += mdss_mdp_splash_logo.o mdss-mdp-objs += mdss_mdp_cdm.o mdss-mdp-objs += mdss_smmu.o mdss-mdp-objs += mdss_mdp_wfd.o mdss-mdp-objs += mdss_io_util.o obj-$(CONFIG_FB_MSM_MDSS) += mdss-mdp.o obj-$(CONFIG_FB_MSM_MDSS) += mdss_mdp_debug.o Loading Loading
drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c +1 −1 Original line number Diff line number Diff line Loading @@ -1141,7 +1141,7 @@ int shadow_pll_vco_set_rate_8996(struct clk *c, unsigned long rate) return rc; } unsigned long pll_vco_get_rate_8996(struct clk *c) static unsigned long pll_vco_get_rate_8996(struct clk *c) { u64 vco_rate, multiplier = BIT(20); s32 div_frac_start; Loading
drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c +7 −7 Original line number Diff line number Diff line Loading @@ -31,14 +31,14 @@ #define HDMI_CLKS_PLL_DIVSEL 0 #define HDMI_CORECLK_DIV 5 #define HDMI_REF_CLOCK 19200000 #define HDMI_64B_ERR_VAL 0xFFFFFFFFFFFFFFFF #define HDMI_64B_ERR_VAL 0xFFFFFFFFFFFFFFFFULL #define HDMI_VERSION_8996_V1 1 #define HDMI_VERSION_8996_V2 2 #define HDMI_VERSION_8996_V3 3 #define HDMI_VERSION_8996_V3_1_8 4 #define HDMI_VCO_MAX_FREQ 12000000000 #define HDMI_VCO_MIN_FREQ 8000000000 #define HDMI_VCO_MAX_FREQ 12000000000UL #define HDMI_VCO_MIN_FREQ 8000000000UL #define HDMI_2400MHZ_BIT_CLK_HZ 2400000000UL #define HDMI_2250MHZ_BIT_CLK_HZ 2250000000UL #define HDMI_2000MHZ_BIT_CLK_HZ 2000000000UL Loading Loading @@ -2566,7 +2566,7 @@ static enum handoff hdmi_8996_vco_handoff(struct clk *c) return ret; } const struct clk_ops hdmi_8996_v1_vco_clk_ops = { static const struct clk_ops hdmi_8996_v1_vco_clk_ops = { .enable = hdmi_8996_v1_vco_enable, .set_rate = hdmi_8996_v1_vco_set_rate, .get_rate = hdmi_8996_vco_get_rate, Loading @@ -2576,7 +2576,7 @@ const struct clk_ops hdmi_8996_v1_vco_clk_ops = { .handoff = hdmi_8996_vco_handoff, }; const struct clk_ops hdmi_8996_v2_vco_clk_ops = { static const struct clk_ops hdmi_8996_v2_vco_clk_ops = { .enable = hdmi_8996_v2_vco_enable, .set_rate = hdmi_8996_v2_vco_set_rate, .get_rate = hdmi_8996_vco_get_rate, Loading @@ -2586,7 +2586,7 @@ const struct clk_ops hdmi_8996_v2_vco_clk_ops = { .handoff = hdmi_8996_vco_handoff, }; const struct clk_ops hdmi_8996_v3_vco_clk_ops = { static const struct clk_ops hdmi_8996_v3_vco_clk_ops = { .enable = hdmi_8996_v3_vco_enable, .set_rate = hdmi_8996_v3_vco_set_rate, .get_rate = hdmi_8996_vco_get_rate, Loading @@ -2596,7 +2596,7 @@ const struct clk_ops hdmi_8996_v3_vco_clk_ops = { .handoff = hdmi_8996_vco_handoff, }; const struct clk_ops hdmi_8996_v3_1p8_vco_clk_ops = { static const struct clk_ops hdmi_8996_v3_1p8_vco_clk_ops = { .enable = hdmi_8996_v3_1p8_vco_enable, .set_rate = hdmi_8996_v3_1p8_vco_set_rate, .get_rate = hdmi_8996_vco_get_rate, Loading
drivers/clk/msm/mdss/mdss-pll-util.c +23 −22 Original line number Diff line number Diff line Loading @@ -28,16 +28,16 @@ int mdss_pll_util_resource_init(struct platform_device *pdev, struct mdss_pll_resources *pll_res) { int rc = 0; struct dss_module_power *mp = &pll_res->mp; struct mdss_module_power *mp = &pll_res->mp; rc = msm_dss_config_vreg(&pdev->dev, rc = msm_mdss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 1); if (rc) { pr_err("Vreg config failed rc=%d\n", rc); goto vreg_err; } rc = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk); rc = msm_mdss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk); if (rc) { pr_err("Clock get failed rc=%d\n", rc); goto clk_err; Loading @@ -46,7 +46,7 @@ int mdss_pll_util_resource_init(struct platform_device *pdev, return rc; clk_err: msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0); msm_mdss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0); vreg_err: return rc; } Loading @@ -59,11 +59,11 @@ int mdss_pll_util_resource_init(struct platform_device *pdev, * This is a helper function to retrieve the regulator information * for each pll resource. */ struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res struct mdss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res , char *name) { struct dss_vreg *regulator = NULL; struct mdss_vreg *regulator = NULL; int i; if ((pll_res == NULL) || (pll_res->mp.vreg_config == NULL)) { Loading @@ -88,17 +88,17 @@ struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res void mdss_pll_util_resource_deinit(struct platform_device *pdev, struct mdss_pll_resources *pll_res) { struct dss_module_power *mp = &pll_res->mp; struct mdss_module_power *mp = &pll_res->mp; msm_dss_put_clk(mp->clk_config, mp->num_clk); msm_mdss_put_clk(mp->clk_config, mp->num_clk); msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0); msm_mdss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0); } void mdss_pll_util_resource_release(struct platform_device *pdev, struct mdss_pll_resources *pll_res) { struct dss_module_power *mp = &pll_res->mp; struct mdss_module_power *mp = &pll_res->mp; devm_kfree(&pdev->dev, mp->clk_config); devm_kfree(&pdev->dev, mp->vreg_config); Loading @@ -110,36 +110,37 @@ int mdss_pll_util_resource_enable(struct mdss_pll_resources *pll_res, bool enable) { int rc = 0; struct dss_module_power *mp = &pll_res->mp; struct mdss_module_power *mp = &pll_res->mp; if (enable) { rc = msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable); rc = msm_mdss_enable_vreg(mp->vreg_config, mp->num_vreg, enable); if (rc) { pr_err("Failed to enable vregs rc=%d\n", rc); goto vreg_err; } rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk); rc = msm_mdss_clk_set_rate(mp->clk_config, mp->num_clk); if (rc) { pr_err("Failed to set clock rate rc=%d\n", rc); goto clk_err; } rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable); rc = msm_mdss_enable_clk(mp->clk_config, mp->num_clk, enable); if (rc) { pr_err("clock enable failed rc:%d\n", rc); goto clk_err; } } else { msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable); msm_mdss_enable_clk(mp->clk_config, mp->num_clk, enable); msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable); msm_mdss_enable_vreg(mp->vreg_config, mp->num_vreg, enable); } return rc; clk_err: msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, 0); msm_mdss_enable_vreg(mp->vreg_config, mp->num_vreg, 0); vreg_err: return rc; } Loading @@ -151,7 +152,7 @@ static int mdss_pll_util_parse_dt_supply(struct platform_device *pdev, u32 tmp = 0; struct device_node *of_node = NULL, *supply_root_node = NULL; struct device_node *supply_node = NULL; struct dss_module_power *mp = &pll_res->mp; struct mdss_module_power *mp = &pll_res->mp; of_node = pdev->dev.of_node; Loading @@ -173,7 +174,7 @@ static int mdss_pll_util_parse_dt_supply(struct platform_device *pdev, } pr_debug("vreg found. count=%d\n", mp->num_vreg); mp->vreg_config = devm_kzalloc(&pdev->dev, sizeof(struct dss_vreg) * mp->vreg_config = devm_kzalloc(&pdev->dev, sizeof(struct mdss_vreg) * mp->num_vreg, GFP_KERNEL); if (!mp->vreg_config) { rc = -ENOMEM; Loading Loading @@ -298,7 +299,7 @@ static int mdss_pll_util_parse_dt_clock(struct platform_device *pdev, struct mdss_pll_resources *pll_res) { u32 i = 0, rc = 0; struct dss_module_power *mp = &pll_res->mp; struct mdss_module_power *mp = &pll_res->mp; const char *clock_name; u32 clock_rate; Loading @@ -310,7 +311,7 @@ static int mdss_pll_util_parse_dt_clock(struct platform_device *pdev, } mp->clk_config = devm_kzalloc(&pdev->dev, sizeof(struct dss_clk) * mp->num_clk, GFP_KERNEL); sizeof(struct mdss_clk) * mp->num_clk, GFP_KERNEL); if (!mp->clk_config) { rc = -ENOMEM; mp->num_clk = 0; Loading Loading @@ -420,7 +421,7 @@ int mdss_pll_util_resource_parse(struct platform_device *pdev, struct mdss_pll_resources *pll_res) { int rc = 0; struct dss_module_power *mp = &pll_res->mp; struct mdss_module_power *mp = &pll_res->mp; rc = mdss_pll_util_parse_dt_supply(pdev, pll_res); if (rc) { Loading
drivers/clk/msm/mdss/mdss-pll.h +3 −3 Original line number Diff line number Diff line /* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. /* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -76,7 +76,7 @@ struct dfps_info { struct mdss_pll_resources { /* Pll specific resources like GPIO, power supply, clocks, etc*/ struct dss_module_power mp; struct mdss_module_power mp; /* * dsi/edp/hmdi plls' base register, phy, gdsc and dynamic refresh Loading Loading @@ -219,6 +219,6 @@ int mdss_pll_util_resource_enable(struct mdss_pll_resources *pll_res, bool enable); int mdss_pll_util_resource_parse(struct platform_device *pdev, struct mdss_pll_resources *pll_res); struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res struct mdss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res , char *name); #endif
drivers/video/fbdev/msm/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -21,6 +21,7 @@ mdss-mdp-objs += mdss_mdp_splash_logo.o mdss-mdp-objs += mdss_mdp_cdm.o mdss-mdp-objs += mdss_smmu.o mdss-mdp-objs += mdss_mdp_wfd.o mdss-mdp-objs += mdss_io_util.o obj-$(CONFIG_FB_MSM_MDSS) += mdss-mdp.o obj-$(CONFIG_FB_MSM_MDSS) += mdss_mdp_debug.o Loading