Merge branch '4.7-fixes' into mips-for-linux-next

   MPX-instrumented.

3) The kernel detects that the CPU has MPX, allows the new prctl() to

   succeed, and notes the location of the bounds directory. Userspace is

   expected to keep the bounds directory at that locationWe note it

   expected to keep the bounds directory at that location. We note it

   instead of reading it each time because the 'xsave' operation needed

   to access the bounds directory register is an expensive operation.

4) If the application needs to spill bounds out of the 4 registers, it

We need to decode MPX instructions to get violation address and

set this address into extended struct siginfo.

The _sigfault feild of struct siginfo is extended as follow:

The _sigfault field of struct siginfo is extended as follow:

87		/* SIGILL, SIGFPE, SIGSEGV, SIGBUS */

88		struct {

This is allowed architecturally.  See more information "Intel(R) Architecture

Instruction Set Extensions Programming Reference" (9.3.4).

However, if users did this, the kernel might be fooled in to unmaping an

However, if users did this, the kernel might be fooled in to unmapping an

in-use bounds table since it does not recognize sharing.

    from areas other than the one we are trying to flush will be

    destroyed and must be refilled later, at some cost.

 2. Use the invlpg instruction to invalidate a single page at a

    time.  This could potentialy cost many more instructions, but

    time.  This could potentially cost many more instructions, but

    it is a much more precise operation, causing no collateral

    damage to other TLB entries.

    work.

 3. The size of the TLB.  The larger the TLB, the more collateral

    damage we do with a full flush.  So, the larger the TLB, the

    more attrative an individual flush looks.  Data and

    more attractive an individual flush looks.  Data and

    instructions have separate TLBs, as do different page sizes.

 4. The microarchitecture.  The TLB has become a multi-level

    cache on modern CPUs, and the global flushes have become more

check_interval

	How often to poll for corrected machine check errors, in seconds

	(Note output is hexademical). Default 5 minutes.  When the poller

	(Note output is hexadecimal). Default 5 minutes.  When the poller

	finds MCEs it triggers an exponential speedup (poll more often) on

	the polling interval.  When the poller stops finding MCEs, it

	triggers an exponential backoff (poll less often) on the polling

VERSION = 4

PATCHLEVEL = 7

SUBLEVEL = 0

EXTRAVERSION = -rc6

EXTRAVERSION = -rc7

NAME = Psychotic Stoned Sheep

# *DOCUMENTATION*

#define APM_CPU_PART_POTENZA		0x000

#define CAVIUM_CPU_PART_THUNDERX	0x0A1

#define CAVIUM_CPU_PART_THUNDERX_81XX	0x0A2

#define BRCM_CPU_PART_VULCAN		0x516

#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)

#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

#ifndef __ASSEMBLY__