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Commit 4f53989b authored by Matt Redfearn's avatar Matt Redfearn Committed by Ralf Baechle
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MIPS: mm: Fix definition of R6 cache instruction 



Commit a168b8f1 ("MIPS: mm: Add MIPS R6 instruction encodings") added
an incorrect definition of the redefined MIPSr6 cache instruction.

Executing any kernel code including this instuction results in a
reserved instruction exception and kernel panic.

Fix the instruction definition.

Fixes: a168b8f1
Signed-off-by: default avatarMatt Redfearn <matt.redfearn@imgtec.com>
Cc: <stable@vger.kernel.org> # 4.x-
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13663/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 828a5428

arch/mips/mm/uasm-mips.c

+1 −1
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ static struct insn insn_table[] = { 
#ifndef CONFIG_CPU_MIPSR6

	{ insn_cache,  M(cache_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },

#else

	{ insn_cache,  M6(cache_op, 0, 0, 0, cache6_op),  RS | RT | SIMM9 },

	{ insn_cache,  M6(spec3_op, 0, 0, 0, cache6_op),  RS | RT | SIMM9 },

#endif

	{ insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },

	{ insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },