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Commit 48ecfa10 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: properly set ppgtt cacheability on snb 



For some reason snb has 2 fields to set ppgtt cacheability. This one
here does not exist on gen7.

This might explain why ppgtt wasn't a win on snb like on ivb - not
enough pte caching.

v2: Fixup rebase fail.

Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent be901a5a

drivers/gpu/drm/i915/i915_gem.c

+4 −1
Original line number Diff line number Diff line
@@ -3669,7 +3669,10 @@ void i915_gem_init_ppgtt(struct drm_device *dev) 
	pd_offset <<= 16;



	if (INTEL_INFO(dev)->gen == 6) {

		uint32_t ecochk, gab_ctl;

		uint32_t ecochk, gab_ctl, ecobits;



		ecobits = I915_READ(GAC_ECO_BITS); 

		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);



		gab_ctl = I915_READ(GAB_CTL);

		I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -127,6 +127,10 @@ 
#define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)

#define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)



#define GAC_ECO_BITS			0x14090

#define   ECOBITS_PPGTT_CACHE64B	(3<<8)

#define   ECOBITS_PPGTT_CACHE4B		(0<<8)



#define GAB_CTL				0x24000

#define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1<<8)