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Commit be901a5a authored Apr 11, 2012 by Daniel Vetter

drm/i915: set w/a bit for snb pagefaults



Bspec says that we need to set this: vol1c.3 "Blitter Command
Streamer", Section 1.1.2.1 "GAB_CTL_REG - GAB Unit Control Register".

We don't really rely on pagefaults, but who knows what this all
affects.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent de4a8bd1

drivers/gpu/drm/i915/i915_gem.c

+6 −1

Original line number	Diff line number	Diff line
		@@ -3669,7 +3669,12 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
		pd_offset <<= 16;

		if (INTEL_INFO(dev)->gen == 6) {
		uint32_t ecochk = I915_READ(GAM_ECOCHK);
		uint32_t ecochk, gab_ctl;

		gab_ctl = I915_READ(GAB_CTL);
		I915_WRITE(GAB_CTL, gab_ctl \| GAB_CTL_CONT_AFTER_PAGEFAULT);

		ecochk = I915_READ(GAM_ECOCHK);
		I915_WRITE(GAM_ECOCHK, ecochk \| ECOCHK_SNB_BIT \|
		ECOCHK_PPGTT_CACHE64B);
		I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));

drivers/gpu/drm/i915/i915_reg.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -127,6 +127,9 @@
		#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
		#define ECOCHK_PPGTT_CACHE4B (0x0<<3)

		#define GAB_CTL 0x24000
		#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)

		/* VGA stuff */

		#define VGA_ST01_MDA 0x3ba