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Commit 484048db authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux into drm-next 

radeon userptr support.

* 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: allow userptr write access under certain conditions
  drm/radeon: add userptr flag to register MMU notifier v3
  drm/radeon: add userptr flag to directly validate the BO to GTT
  drm/radeon: add userptr flag to limit it to anonymous memory v2
  drm/radeon: add userptr support v8

Conflicts:
	drivers/gpu/drm/radeon/radeon_prime.c
parents d5a0f2e7 bd645e43

drivers/gpu/drm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -116,6 +116,7 @@ config DRM_RADEON 
	select HWMON

	select BACKLIGHT_CLASS_DEVICE

	select INTERVAL_TREE

	select MMU_NOTIFIER

	help

	  Choose this option if you have an ATI Radeon graphics card.  There

	  are both PCI and AGP versions.  You don't need to choose this to

drivers/gpu/drm/radeon/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ 
	r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \

	rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \

	trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \

	ci_dpm.o dce6_afmt.o radeon_vm.o radeon_ucode.o radeon_ib.o

	ci_dpm.o dce6_afmt.o radeon_vm.o radeon_ucode.o radeon_ib.o radeon_mn.o



# add async DMA block

radeon-y += \

drivers/gpu/drm/radeon/radeon.h

+18 −0
Original line number Diff line number Diff line
@@ -65,6 +65,7 @@ 
#include <linux/list.h>

#include <linux/kref.h>

#include <linux/interval_tree.h>

#include <linux/hashtable.h>



#include <ttm/ttm_bo_api.h>

#include <ttm/ttm_bo_driver.h>
@@ -488,6 +489,9 @@ struct radeon_bo { 


	struct ttm_bo_kmap_obj		dma_buf_vmap;

	pid_t				pid;



	struct radeon_mn		*mn;

	struct interval_tree_node	mn_it;

};

#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
@@ -1728,6 +1732,11 @@ void radeon_test_ring_sync(struct radeon_device *rdev, 
			   struct radeon_ring *cpB);

void radeon_test_syncing(struct radeon_device *rdev);



/*

 * MMU Notifier

 */

int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);

void radeon_mn_unregister(struct radeon_bo *bo);



/*

 * Debugfs
@@ -2141,6 +2150,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 
			  struct drm_file *filp);

int radeon_gem_create_ioctl(struct drm_device *dev, void *data,

			    struct drm_file *filp);

int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,

			     struct drm_file *filp);

int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,

			 struct drm_file *file_priv);

int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
@@ -2373,6 +2384,9 @@ struct radeon_device { 
	/* tracking pinned memory */

	u64 vram_pin_size;

	u64 gart_pin_size;



	struct mutex	mn_lock;

	DECLARE_HASHTABLE(mn_hash, 7);

};



bool radeon_is_px(struct drm_device *dev);
@@ -2874,6 +2888,10 @@ extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enabl 
extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);

extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);

extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);

extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,

				     uint32_t flags);

extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);

extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);

extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);

extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);

extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);

drivers/gpu/drm/radeon/radeon_cs.c

+23 −2
Original line number Diff line number Diff line
@@ -78,7 +78,8 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) 
	struct radeon_cs_chunk *chunk;

	struct radeon_cs_buckets buckets;

	unsigned i, j;

	bool duplicate;

	bool duplicate, need_mmap_lock = false;

	int r;



	if (p->chunk_relocs_idx == -1) {

		return 0;
@@ -165,6 +166,19 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) 
			p->relocs[i].allowed_domains = domain;

		}



		if (radeon_ttm_tt_has_userptr(p->relocs[i].robj->tbo.ttm)) {

			uint32_t domain = p->relocs[i].prefered_domains;

			if (!(domain & RADEON_GEM_DOMAIN_GTT)) {

				DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is "

					  "allowed for userptr BOs\n");

				return -EINVAL;

			}

			need_mmap_lock = true;

			domain = RADEON_GEM_DOMAIN_GTT;

			p->relocs[i].prefered_domains = domain;

			p->relocs[i].allowed_domains = domain;

		}



		p->relocs[i].tv.bo = &p->relocs[i].robj->tbo;

		p->relocs[i].handle = r->handle;
@@ -177,8 +191,15 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) 
	if (p->cs_flags & RADEON_CS_USE_VM)

		p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm,

					      &p->validated);

	if (need_mmap_lock)

		down_read(&current->mm->mmap_sem);



	r = radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring);



	return radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring);

	if (need_mmap_lock)

		up_read(&current->mm->mmap_sem);



	return r;

}



static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)

drivers/gpu/drm/radeon/radeon_device.c

+2 −0
Original line number Diff line number Diff line
@@ -1270,6 +1270,8 @@ int radeon_device_init(struct radeon_device *rdev, 
	init_rwsem(&rdev->pm.mclk_lock);

	init_rwsem(&rdev->exclusive_lock);

	init_waitqueue_head(&rdev->irq.vblank_queue);

	mutex_init(&rdev->mn_lock);

	hash_init(rdev->mn_hash);

	r = radeon_gem_init(rdev);

	if (r)

		return r;