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Commit d5a0f2e7 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2014-08-08' of git://anongit.freedesktop.org/drm-intel into drm-next 

- Setting dp M2/N2 values plus state checker support (Vandana Kannan)
- chv power well support (Ville)
- DP training pattern 3 support for chv (Ville)
- cleanup of the hsw/bdw ddi pll code, prep work for skl (Damien)
- dsi video burst mode support (Shobhit)
- piles of other chv fixes all over (Ville et. al.)
- cleanup of the ddi translation tables setup code (Damien)
- 180 deg rotation support (Ville & Sonika Jindal)

* tag 'drm-intel-next-2014-08-08' of git://anongit.freedesktop.org/drm-intel: (59 commits)
  drm/i915: Update DRIVER_DATE to 20140808
  drm/i915: No busy-loop wait_for in the ring init code
  drm/i915: Add sprite watermark programming for VLV and CHV
  drm/i915: Round-up clock and limit drain latency
  drm/i915: Generalize drain latency computation
  drm/i915: Free pending page flip events at .preclose()
  drm/i915: clean up PPGTT checking logic
  drm/i915: Polish the chv cmnlane resrt macros
  drm/i915: Hack to tie both common lanes together on chv
  drm/i915: Add cherryview_update_wm()
  drm/i915: Update DDL only for current CRTC
  drm/i915: Parametrize VLV_DDL registers
  drm/i915: Fill out the FWx watermark register defines
  drm: Resetting rotation property
  drm/i915: Add rotation property for sprites
  drm: Add rotation_property to mode_config
  drm/i915: Make intel_plane_restore() return an error
  drm/i915: Add 180 degree sprite rotation support
  drm/i915: Introduce a for_each_intel_encoder() macro
  drm/i915: Demote the DRRS messages to debug messages
  ...
parents c0ee755f 2c0827cf

Documentation/DocBook/drm.tmpl

+1 −0
Original line number Diff line number Diff line
@@ -3400,6 +3400,7 @@ void (*disable_vblank) (struct drm_device *dev, int crtc);</synopsis> 
    <sect2>

      <title>Vertical Blanking and Interrupt Handling Functions Reference</title>

!Edrivers/gpu/drm/drm_irq.c

!Iinclude/drm/drmP.h drm_crtc_vblank_waitqueue

    </sect2>

  </sect1>

drivers/gpu/drm/drm_fb_helper.c

+8 −1
Original line number Diff line number Diff line
@@ -291,10 +291,17 @@ static bool restore_fbdev_mode(struct drm_fb_helper *fb_helper) 


	drm_warn_on_modeset_not_all_locked(dev);



	list_for_each_entry(plane, &dev->mode_config.plane_list, head)

	list_for_each_entry(plane, &dev->mode_config.plane_list, head) {

		if (plane->type != DRM_PLANE_TYPE_PRIMARY)

			drm_plane_force_disable(plane);



		if (dev->mode_config.rotation_property) {

			drm_object_property_set_value(&plane->base,

					dev->mode_config.rotation_property,

					BIT(DRM_ROTATE_0));

		}

	}



	for (i = 0; i < fb_helper->crtc_count; i++) {

		struct drm_mode_set *mode_set = &fb_helper->crtc_info[i].mode_set;

		struct drm_crtc *crtc = mode_set->crtc;

drivers/gpu/drm/i915/i915_debugfs.c

+43 −2
Original line number Diff line number Diff line
@@ -1433,6 +1433,47 @@ static int i915_fbc_status(struct seq_file *m, void *unused) 
	return 0;

}



static int i915_fbc_fc_get(void *data, u64 *val)

{

	struct drm_device *dev = data;

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))

		return -ENODEV;



	drm_modeset_lock_all(dev);

	*val = dev_priv->fbc.false_color;

	drm_modeset_unlock_all(dev);



	return 0;

}



static int i915_fbc_fc_set(void *data, u64 val)

{

	struct drm_device *dev = data;

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 reg;



	if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))

		return -ENODEV;



	drm_modeset_lock_all(dev);



	reg = I915_READ(ILK_DPFC_CONTROL);

	dev_priv->fbc.false_color = val;



	I915_WRITE(ILK_DPFC_CONTROL, val ?

		   (reg | FBC_CTL_FALSE_COLOR) :

		   (reg & ~FBC_CTL_FALSE_COLOR));



	drm_modeset_unlock_all(dev);

	return 0;

}



DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,

			i915_fbc_fc_get, i915_fbc_fc_set,

			"%llu\n");



static int i915_ips_status(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = m->private;
@@ -2667,8 +2708,7 @@ static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, 
	*source = INTEL_PIPE_CRC_SOURCE_PIPE;



	drm_modeset_lock_all(dev);

	list_for_each_entry(encoder, &dev->mode_config.encoder_list,

			    base.head) {

	for_each_intel_encoder(dev, encoder) {

		if (!encoder->base.crtc)

			continue;
@@ -3957,6 +3997,7 @@ static const struct i915_debugfs_files { 
	{"i915_pri_wm_latency", &i915_pri_wm_latency_fops},

	{"i915_spr_wm_latency", &i915_spr_wm_latency_fops},

	{"i915_cur_wm_latency", &i915_cur_wm_latency_fops},

	{"i915_fbc_false_color", &i915_fbc_fc_fops},

};



void intel_display_crc_init(struct drm_device *dev)

drivers/gpu/drm/i915/i915_dma.c

+3 −0
Original line number Diff line number Diff line
@@ -1981,6 +1981,9 @@ void i915_driver_preclose(struct drm_device *dev, struct drm_file *file) 
	i915_gem_context_close(dev, file);

	i915_gem_release(dev, file);

	mutex_unlock(&dev->struct_mutex);



	if (drm_core_check_feature(dev, DRIVER_MODESET))

		intel_modeset_preclose(dev, file);

}



void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)

drivers/gpu/drm/i915/i915_drv.h

+19 −3
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ 


#define DRIVER_NAME		"i915"

#define DRIVER_DESC		"Intel Graphics"

#define DRIVER_DATE		"20140725"

#define DRIVER_DATE		"20140808"



enum pipe {

	INVALID_PIPE = -1,
@@ -171,6 +171,11 @@ enum hpd_pin { 
#define for_each_intel_crtc(dev, intel_crtc) \

	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)



#define for_each_intel_encoder(dev, intel_encoder)		\

	list_for_each_entry(intel_encoder,			\

			    &(dev)->mode_config.encoder_list,	\

			    base.head)



#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \

	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \

		if ((intel_encoder)->base.crtc == (__crtc))
@@ -197,10 +202,13 @@ enum intel_dpll_id { 
#define I915_NUM_PLLS 2



struct intel_dpll_hw_state {

	/* i9xx, pch plls */

	uint32_t dpll;

	uint32_t dpll_md;

	uint32_t fp0;

	uint32_t fp1;



	/* hsw, bdw */

	uint32_t wrpll;

};
@@ -634,6 +642,8 @@ struct i915_fbc { 
	struct drm_mm_node compressed_fb;

	struct drm_mm_node *compressed_llb;



	bool false_color;



	struct intel_fbc_work {

		struct delayed_work work;

		struct drm_crtc *crtc;
@@ -1227,6 +1237,12 @@ enum modeset_restore { 
};



struct ddi_vbt_port_info {

	/*

	 * This is an index in the HDMI/DVI DDI buffer translation table.

	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't

	 * populate this field.

	 */

#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff

	uint8_t hdmi_level_shift;



	uint8_t supports_dvi:1;
@@ -2049,8 +2065,8 @@ struct drm_i915_cmd_table { 
#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)

#define HAS_ALIASING_PPGTT(dev)	(INTEL_INFO(dev)->gen >= 6)

#define HAS_PPGTT(dev)		(INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev))

#define USES_PPGTT(dev)		intel_enable_ppgtt(dev, false)

#define USES_FULL_PPGTT(dev)	intel_enable_ppgtt(dev, true)

#define USES_PPGTT(dev)		(i915.enable_ppgtt)

#define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt == 2)



#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)

#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)