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Commit 44395bfe authored by Durgadoss R's avatar Durgadoss R Committed by Daniel Vetter
Browse files

drm/i915: Enable eDP DRRS for CHV 



This patch enables eDP DRRS for CHV by adding the
required IS_CHERRYVIEW() checks.
CHV uses the same register bit as VLV.

[Vandana]: Since CHV has 2 sets of M_N registers, it will follow the same code
path as gen < 8. Added CHV check in dp_set_m_n()

[Ram]: Rebased on top of previous patch modifications

Signed-off-by: default avatarDurgadoss R <durgadoss.r@intel.com>
Signed-off-by: default avatarVandana Kannan <vandana.kannan@intel.com>
Signed-off-by: default avatarRamalingam C <ramalingam.c@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 6fa7aec1

drivers/gpu/drm/i915/intel_display.c

+1 −1
Original line number Diff line number Diff line
@@ -5879,7 +5879,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, 
		 * for gen < 8) and if DRRS is supported (to make sure the

		 * registers are not unnecessarily accessed).

		 */

		if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&

		if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&

			crtc->config->has_drrs) {

			I915_WRITE(PIPE_DATA_M2(transcoder),

					TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);

drivers/gpu/drm/i915/intel_dp.c

+1 −1
Original line number Diff line number Diff line
@@ -4808,7 +4808,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) 
		return;

	}



	if (INTEL_INFO(dev)->gen >= 8) {

	if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {

		switch (index) {

		case DRRS_HIGH_RR:

			intel_dp_set_m_n(intel_crtc, M1_N1);