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Commit 4305f424 authored by Linus Torvalds's avatar Linus Torvalds
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Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for MIPS for 4.8.  Also includes is a
  minor SSB cleanup as SSB code traditionally is merged through the MIPS
  tree:

  ATH25:
    - MIPS: Add default configuration for ath25

  Boot:
    - For zboot, copy appended dtb to the end of the kernel
    - store the appended dtb address in a variable

  BPF:
    - Fix off by one error in offset allocation

  Cobalt code:
    - Fix typos

  Core code:
    - debugfs_create_file returns NULL on error, so don't use IS_ERR for
      testing for errors.
    - Fix double locking issue in RM7000 S-cache code.  This would only
      affect RM7000 ARC systems on reboot.
    - Fix page table corruption on THP permission changes.
    - Use compat_sys_keyctl for 32 bit userspace on 64 bit kernels.
      David says, there are no compatibility issues raised by this fix.
    - Move some signal code around.
    - Rewrite r4k count/compare clockevent device registration such that
      min_delta_ticks/max_delta_ticks files are guaranteed to be
      initialized.
    - Only register r4k count/compare as clockevent device if we can
      assume the clock to be constant.
    - Fix MSA asm warnings in control reg accessors
    - uasm and tlbex fixes and tweaking.
    - Print segment physical address when EU=1.
    - Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO.
    - CP: Allow booting by VP other than VP 0
    - Cache handling fixes and optimizations for r4k class caches
    - Add hotplug support for R6 processors
    - Cleanup hotplug bits in kconfig
    - traps: return correct si code for accessing nonmapped addresses
    - Remove cpu_has_safe_index_cacheops

  Lantiq:
    - Register IRQ handler for virtual IRQ number
    - Fix EIU interrupt loading code
    - Use the real EXIN count
    - Fix build error.

  Loongson 3:
    - Increase HPET_MIN_PROG_DELTA and decrease HPET_MIN_CYCLES

  Octeon:
    - Delete built-in DTB pruning code for D-Link DSR-1000N.
    - Clean up GPIO definitions in dlink_dsr-1000n.dts.
    - Add more LEDs to the DSR-100n DTS
    - Fix off by one in octeon_irq_gpio_map()
    - Typo fixes
    - Enable SATA by default in cavium_octeon_defconfig
    - Support readq/writeq()
    - Remove forced mappings of USB interrupts.
    - Ensure DMA descriptors are always in the low 4GB
    - Improve USB reset code for OCTEON II.

  Pistachio:
    - Add maintainers entry for pistachio SoC Support
    - Remove plat_setup_iocoherency

  Ralink:
    - Fix pwm UART in spis group pinmux.

  SSB:
    - Change bare unsigned to unsigned int to suit coding style

  Tools:
    - Fix reloc tool compiler warnings.

  Other:
    - Delete use of ARCH_WANT_OPTIONAL_GPIOLIB"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (61 commits)
  MIPS: mm: Fix definition of R6 cache instruction
  MIPS: tools: Fix relocs tool compiler warnings
  MIPS: Cobalt: Fix typo
  MIPS: Octeon: Fix typo
  MIPS: Lantiq: Fix build failure
  MIPS: Use CPHYSADDR to implement mips32 __pa
  MIPS: Octeon: Dlink_dsr-1000n.dts: add more leds.
  MIPS: Octeon: Clean up GPIO definitions in dlink_dsr-1000n.dts.
  MIPS: Octeon: Delete built-in DTB pruning code for D-Link DSR-1000N.
  MIPS: store the appended dtb address in a variable
  MIPS: ZBOOT: copy appended dtb to the end of the kernel
  MIPS: ralink: fix spis group pinmux
  MIPS: Factor o32 specific code into signal_o32.c
  MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present
  MIPS: Use per-mm page to execute branch delay slot instructions
  MIPS: Modify error handling
  MIPS: c-r4k: Use SMP calls for CM indexed cache ops
  MIPS: c-r4k: Avoid small flush_icache_range SMP calls
  MIPS: c-r4k: Local flush_icache_range cache op override
  MIPS: c-r4k: Split r4k_flush_kernel_vmap_range()
  ...
parents db826278 4a89cf81
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+10 −0
Original line number Diff line number Diff line
@@ -9252,6 +9252,16 @@ W: http://www.st.com/spear
S:	Maintained
F:	drivers/pinctrl/spear/

PISTACHIO SOC SUPPORT
M:      James Hartley <james.hartley@imgtec.com>
M:      Ionela Voinescu <ionela.voinescu@imgtec.com>
L:      linux-mips@linux-mips.org
S:      Maintained
F:      arch/mips/pistachio/
F:      arch/mips/include/asm/mach-pistachio/
F:      arch/mips/boot/dts/pistachio/
F:      arch/mips/configs/pistachio*_defconfig

PKTCDVD DRIVER
M:	Jiri Kosina <jikos@kernel.org>
S:	Maintained
+14 −33
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ config MIPS
	select GENERIC_TIME_VSYSCALL
	select ARCH_CLOCKSOURCE_DATA
	select HANDLE_DOMAIN_IRQ
	select HAVE_EXIT_THREAD

menu "Machine selection"

@@ -384,7 +385,7 @@ config MACH_PISTACHIO
	select CLKSRC_MIPS_GIC
	select COMMON_CLK
	select CSRC_R4K
	select DMA_MAYBE_COHERENT
	select DMA_NONCOHERENT
	select GPIOLIB
	select IRQ_MIPS_CPU
	select LIBFDT
@@ -880,7 +881,6 @@ config CAVIUM_OCTEON_SOC
	select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
	select SYS_HAS_EARLY_PRINTK
	select SYS_HAS_CPU_CAVIUM_OCTEON
	select SWAP_IO_SPACE
	select HW_HAS_PCI
	select ZONE_DMA32
	select HOLES_IN_ZONE
@@ -1111,16 +1111,6 @@ config NEED_DMA_MAP_STATE
config SYS_HAS_EARLY_PRINTK
	bool

config HOTPLUG_CPU
	bool "Support for hot-pluggable CPUs"
	depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
	help
	  Say Y here to allow turning CPUs off and on. CPUs can be
	  controlled through /sys/devices/system/cpu.
	  (Note: power management support will enable this option
	    automatically on SMP systems. )
	  Say N if you want to disable CPU hotplug.

config SYS_SUPPORTS_HOTPLUG_CPU
	bool

@@ -1406,7 +1396,6 @@ config CPU_LOONGSON1B
	bool "Loongson 1B"
	depends on SYS_HAS_CPU_LOONGSON1B
	select CPU_LOONGSON1
	select ARCH_WANT_OPTIONAL_GPIOLIB
	select LEDS_GPIO_REGISTER
	help
	  The Loongson 1B is a 32-bit SoC, which implements the MIPS32
@@ -2636,6 +2625,16 @@ config SMP

	  If you don't know what to do here, say N.

config HOTPLUG_CPU
	bool "Support for hot-pluggable CPUs"
	depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
	help
	  Say Y here to allow turning CPUs off and on. CPUs can be
	  controlled through /sys/devices/system/cpu.
	  (Note: power management support will enable this option
	    automatically on SMP systems. )
	  Say N if you want to disable CPU hotplug.

config SMP_UP
	bool

@@ -2887,10 +2886,10 @@ choice
		  the documented boot protocol using a device tree.

	config MIPS_RAW_APPENDED_DTB
		bool "vmlinux.bin"
		bool "vmlinux.bin or vmlinuz.bin"
		help
		  With this option, the boot code will look for a device tree binary
		  DTB) appended to raw vmlinux.bin (without decompressor).
		  DTB) appended to raw vmlinux.bin or vmlinuz.bin.
		  (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).

		  This is meant as a backward compatibility convenience for those
@@ -2902,24 +2901,6 @@ choice
		  look like a DTB header after a reboot if no actual DTB is appended
		  to vmlinux.bin.  Do not leave this option active in a production kernel
		  if you don't intend to always append a DTB.

	config MIPS_ZBOOT_APPENDED_DTB
		bool "vmlinuz.bin"
		depends on SYS_SUPPORTS_ZBOOT
		help
		  With this option, the boot code will look for a device tree binary
		  DTB) appended to raw vmlinuz.bin (with decompressor).
		  (e.g. cat vmlinuz.bin <filename>.dtb > vmlinuz_w_dtb).

		  This is meant as a backward compatibility convenience for those
		  systems with a bootloader that can't be upgraded to accommodate
		  the documented boot protocol using a device tree.

		  Beware that there is very little in terms of protection against
		  this option being confused by leftover garbage in memory that might
		  look like a DTB header after a reboot if no actual DTB is appended
		  to vmlinuz.bin.  Do not leave this option active in a production kernel
		  if you don't intend to always append a DTB.
endchoice

choice
+2 −2
Original line number Diff line number Diff line
@@ -203,8 +203,8 @@ void __init plat_mem_setup(void)
	fdt_start = fw_getenvl("fdt_start");
	if (fdt_start)
		__dt_setup_arch((void *)KSEG0ADDR(fdt_start));
	else if (fw_arg0 == -2)
		__dt_setup_arch((void *)KSEG0ADDR(fw_arg1));
	else if (fw_passed_dtb)
		__dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));

	if (mips_machtype != ATH79_MACH_GENERIC_OF) {
		ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
+2 −2
Original line number Diff line number Diff line
@@ -162,8 +162,8 @@ void __init plat_mem_setup(void)
	/* intended to somewhat resemble ARM; see Documentation/arm/Booting */
	if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
		dtb = phys_to_virt(fw_arg2);
	else if (fw_arg0 == -2) /* UHI interface */
		dtb = (void *)fw_arg1;
	else if (fw_passed_dtb) /* UHI interface */
		dtb = (void *)fw_passed_dtb;
	else if (__dtb_start != __dtb_end)
		dtb = (void *)__dtb_start;
	else
+17 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/libfdt.h>

#include <asm/addrspace.h>

@@ -36,6 +37,8 @@ extern void puthex(unsigned long long val);
#define puthex(val) do {} while (0)
#endif

extern char __appended_dtb[];

void error(char *x)
{
	puts("\n\n");
@@ -114,6 +117,20 @@ void decompress_kernel(unsigned long boot_heap_start)
	__decompress((char *)zimage_start, zimage_size, 0, 0,
		   (void *)VMLINUX_LOAD_ADDRESS_ULL, 0, 0, error);

	if (IS_ENABLED(CONFIG_MIPS_RAW_APPENDED_DTB) &&
	    fdt_magic((void *)&__appended_dtb) == FDT_MAGIC) {
		unsigned int image_size, dtb_size;

		dtb_size = fdt_totalsize((void *)&__appended_dtb);

		/* last four bytes is always image size in little endian */
		image_size = le32_to_cpup((void *)&__image_end - 4);

		/* copy dtb to where the booted kernel will expect it */
		memcpy((void *)VMLINUX_LOAD_ADDRESS_ULL + image_size,
		       __appended_dtb, dtb_size);
	}

	/* FIXME: should we flush cache here? */
	puts("Now, booting the kernel...\n");
}
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